add offline charger sepolicy

treble: Set TARGET_NO_KERNEL_OVERRIDE
Taken from Lineage generic targets - skips building kernel cleanly Change-Id: Id71d3a3aed56fd4e815a64ef4191b125fc5026ce
2022-09-21 15:45:32 +02:00 · 2022-09-21 15:45:30 +02:00 · 2022-09-21 15:45:27 +02:00 · 2022-09-21 15:45:19 +02:00
22 changed files with 2254 additions and 29 deletions
--- a/base.mk
+++ b/base.mk
@ -13,6 +13,7 @@ PRODUCT_COPY_FILES += \
 	device/sample/etc/apns-full-conf.xml:system/etc/apns-conf.xml

 BOARD_PLAT_PRIVATE_SEPOLICY_DIR += device/phh/treble/sepolicy
+
 PRODUCT_PACKAGE_OVERLAYS += device/phh/treble/overlay

 $(call inherit-product, vendor/hardware_overlay/overlay.mk)
@ -51,7 +52,11 @@ PRODUCT_COPY_FILES += \
 #   vendor/etc
 PRODUCT_COPY_FILES += \
 	device/phh/treble/nfc/libnfc-nci.conf:system/phh/libnfc-nci-oreo.conf \
-	device/phh/treble/nfc/libnfc-nci-huawei.conf:system/phh/libnfc-nci-huawei.conf
+	device/phh/treble/nfc/libnfc-nci-huawei.conf:system/phh/libnfc-nci-huawei.conf  \
+	device/phh/treble/nfc/libnfc-nci-hi6250-pra.conf:system/phh/libnfc-nci-hi6250-pra.conf \
+	device/phh/treble/nfc/libnfc-brcm-hi6250-pra.conf:system/phh/libnfc-brcm-hi6250-pra.conf \
+	device/phh/treble/nfc/libnfc-nxp_RF-hi6250-pra.conf:system/phh/libnfc-nxp_RF-hi6250-pra.conf \
+	device/phh/treble/nfc/libnfc-nxp-hi6250-pra.conf:system/phh/libnfc-nxp-hi6250-pra.conf

 # LineageOS build may need this to make NFC work
 PRODUCT_PACKAGES += \
@ -61,6 +66,9 @@ PRODUCT_COPY_FILES += \
 	device/phh/treble/rw-system.sh:system/bin/rw-system.sh \
 	device/phh/treble/phh-on-data.sh:system/bin/phh-on-data.sh \
 	device/phh/treble/phh-prop-handler.sh:system/bin/phh-prop-handler.sh \
+	device/phh/treble/secure.sh:system/phh/secure.sh \
+	device/phh/treble/phh.superuser.apk:system/phh/phh.superuser.apk \
+	device/phh/treble/su/su:system/phh/xbin/su \
 	device/phh/treble/fixSPL/getSPL.arm:system/bin/getSPL

 PRODUCT_COPY_FILES += \
@ -74,6 +82,10 @@ PRODUCT_PACKAGES += \
 	bootctl \
 	vintf \

+# add usefull symlinks
+PRODUCT_PACKAGES += \
+	busybox-links
+
 # Fix Offline Charging on Huawmeme
 PRODUCT_PACKAGES += \
 	huawei-charger
--- a/board-base.mk
+++ b/board-base.mk
@ -7,3 +7,7 @@ BOARD_ROOT_EXTRA_FOLDERS += bt_firmware sec_storage efs persist
 BUILD_BROKEN_ELF_PREBUILT_PRODUCT_COPY_FILES := true

 BOARD_ROOT_EXTRA_SYMLINKS := $(filter-out $(BOARD_ROOT_EXTRA_SYMLINKS),/mnt/vendor/persist:/persist)
+
+BOARD_EXT4_SHARE_DUP_BLOCKS := true
+
+TARGET_NO_KERNEL_OVERRIDE := true
--- a/busybox_links/Android.mk
+++ b/busybox_links/Android.mk
@ -0,0 +1,14 @@
+include $(CLEAR_VARS)
+
+LOCAL_MODULE := busybox-links
+LOCAL_MODULE_TAGS := optional
+
+BUSYBOX_BINARY := busybox_phh
+BUSYBOX_SYMLINKS := vi vim xzcat unxz xz arp getty wget telnet traceroute sendmail less fdisk
+
+LOCAL_POST_INSTALL_CMD := \
+    $(hide) mkdir -p system/bin && \
+    $(foreach t,$(BUSYBOX_SYMLINKS),ln -sf $(BUSYBOX_BINARY) system/bin/$(t);)
+#ln -sf busybox_phh $(PRODUCT_OUT)/system/bin/fdisk
+
+include $(BUILD_PHONY_PACKAGE)
--- a/generate.sh
+++ b/generate.sh
@ -17,7 +17,7 @@ echo 'PRODUCT_MAKEFILES := \' > AndroidProducts.mk
 for part in a ab;do
 	for apps in vanilla gapps foss gapps-go;do
 		for arch in arm64 arm a64;do
-			for su in yes no;do
+			for su in yes no z;do
 				apps_suffix=""
 				apps_script=""
 				apps_name=""
@ -56,6 +56,10 @@ for part in a ab;do
 					su_suffix='S'
 					extra_packages+=' phh-su me.phh.superuser'
 				fi
+				if [ "$su" == "z" ];then
+					su_suffix='Z'
+					extra_packages+='zerodaemon'
+				fi

 				part_suffix='a'
 				if [ "$part" == 'ab' ];then
--- a/nfc/libnfc-brcm-hi6250-pra.conf
+++ b/nfc/libnfc-brcm-hi6250-pra.conf
@ -0,0 +1,404 @@
+###################### Start of libnfc-common.conf #######################
+
+###############################################################################
+# Application options
+APPL_TRACE_LEVEL=0xFF
+PROTOCOL_TRACE_LEVEL=0xFFFFFFFF
+
+###############################################################################
+# performance measurement
+# Change this setting to control how often USERIAL log the performance (throughput)
+# data on read/write/poll
+# defailt is to log performance dara for every 100 read or write
+#REPORT_PERFORMANCE_MEASURE=100
+
+###############################################################################
+# File used for NFA storage
+NFA_STORAGE="/data/nfc"
+
+###############################################################################
+# Snooze Mode Settings
+#
+#  By default snooze mode is enabled.  Set SNOOZE_MODE_CFG byte[0] to 0
+#  to disable.
+#
+#  If SNOOZE_MODE_CFG is not provided, the default settings are used:
+#  They are as follows:
+#       8             Sleep Mode (0=Disabled 1=UART 8=SPI/I2C)
+#       0             Idle Threshold Host
+#       0             Idle Threshold HC
+#       0             NFC Wake active mode (0=ActiveLow 1=ActiveHigh)
+#       1             Host Wake active mode (0=ActiveLow 1=ActiveHigh)
+#
+#SNOOZE_MODE_CFG={08:00:00:00:01}
+
+###############################################################################
+# Insert a delay in milliseconds after NFC_WAKE and before write to NFCC
+#NFC_WAKE_DELAY=20
+
+###############################################################################
+# Various Delay settings (in ms) used in USERIAL
+#  POWER_ON_DELAY
+#    Delay after turning on chip, before writing to transport (default 300)
+#  PRE_POWER_OFF_DELAY
+#    Delay after deasserting NFC-Wake before turn off chip (default 0)
+#  POST_POWER_OFF_DELAY
+#    Delay after turning off chip, before USERIAL_close returns (default 0)
+#
+#POWER_ON_DELAY=300
+#PRE_POWER_OFF_DELAY=0
+#POST_POWER_OFF_DELAY=0
+
+###############################################################################
+# Maximum time (ms) to wait for RESET NTF after setting REG_PU to high
+# The default is 1000.
+#NFCC_ENABLE_TIMEOUT=0
+
+###############################################################################
+# LPTD mode configuration
+#  byte[0] is the length of the remaining bytes in this value
+#     if set to 0, LPTD params will NOT be sent to NFCC (i.e. disabled).
+#  byte[1] is the param id it should be set to B9.
+#  byte[2] is the length of the LPTD parameters
+#  byte[3] indicates if LPTD is enabled
+#     if set to 0, LPTD will be disabled (parameters will still be sent).
+#  byte[4-n] are the LPTD parameters.
+#  By default, LPTD is enabled and default settings are used.
+#  See nfc_hal_dm_cfg.c for defaults
+#LPTD_CFG={23:B9:21:01:02:FF:FF:04:A0:0F:40:00:80:02:02:10:00:00:00:31:0C:30:00:00:00:00:00:00:00:00:00:00:00:00:00:00}
+
+###############################################################################
+# Startup Configuration (100 bytes maximum)
+#
+# For the 0xCA parameter, byte[9] (marked by 'AA') is for UICC0, and byte[10] (marked by BB) is
+#    for UICC1.  The values are defined as:
+#   0 : UICCx only supports ISO_DEP in low power mode.
+#   2 : UICCx only supports Mifare in low power mode.
+#   3 : UICCx supports both ISO_DEP and Mifare in low power mode.
+#
+#                                                                          AA BB
+#NFA_DM_START_UP_CFG={1F:CB:01:01:A5:01:01:CA:14:00:00:00:00:06:E8:03:00:00:00:00:00:00:00:00:00:00:00:00:00:80:01:01}
+
+###############################################################################
+# Startup Vendor Specific Configuration (100 bytes maximum);
+#  byte[0] TLV total len = 0x5
+#  byte[1] NCI_MTS_CMD|NCI_GID_PROP = 0x2f
+#  byte[2] NCI_MSG_FRAME_LOG = 0x9
+#  byte[3] 2
+#  byte[4] 0=turn off RF frame logging; 1=turn on
+#  byte[5] 0=turn off SWP frame logging; 1=turn on
+#  NFA_DM_START_UP_VSC_CFG={05:2F:09:02:01:01}
+
+###############################################################################
+# Antenna Configuration - This data is used when setting 0xC8 config item
+# at startup (before discovery is started).  If not used, no value is sent.
+#
+# The settings for this value are documented here:
+# http://wcgbu.broadcom.com/wpan/PM/Project%20Document%20Library/bcm20791B0/
+#   Design/Doc/PHY%20register%20settings/BCM20791-B2-1027-02_PHY_Recommended_Reg_Settings.xlsx
+# This document is maintained by Paul Forshaw.
+#
+# The values marked as ?? should be tweaked per antenna or customer/app:
+# {20:C8:1E:06:??:00:??:??:??:00:??:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:??:01:00:00:40:04}
+# array[0] = 0x20 is length of the payload from array[1] to the end
+# array[1] = 0xC8 is PREINIT_DSP_CFG
+#PREINIT_DSP_CFG={20:C8:1E:06:1F:00:0F:03:3C:00:04:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:48:01:00:00:40:04}
+
+###############################################################################
+# Configure crystal frequency when internal LPO can't detect the frequency.
+#XTAL_FREQUENCY=0
+###############################################################################
+# Configure the default Destination Gate used by HCI (the default is 4, which
+# is the ETSI loopback gate.
+NFA_HCI_DEFAULT_DEST_GATE=0xF0
+
+###############################################################################
+# Configure the single default SE to use.  The default is to use the first
+# SE that is detected by the stack.  This value might be used when the phone
+# supports multiple SE (e.g. 0xF3 and 0xF4) but you want to force it to use
+# one of them (e.g. 0xF4).
+#ACTIVE_SE=0xF3
+
+###############################################################################
+# Configure the default NfcA/IsoDep techology and protocol route. Can be
+# either a secure element (e.g. 0xF4) or the host (0x00)
+#DEFAULT_ISODEP_ROUTE=0x00
+
+###############################################################################
+# Configure the NFC Extras to open and use a static pipe.  If the value is
+# not set or set to 0, then the default is use a dynamic pipe based on a
+# destination gate (see NFA_HCI_DEFAULT_DEST_GATE).  Note there is a value
+# for each UICC (where F3="UICC0" and F4="UICC1")
+#NFA_HCI_STATIC_PIPE_ID_F3=0x70
+#NFA_HCI_STATIC_PIPE_ID_01=0x19
+NFA_HCI_STATIC_PIPE_ID_C0=0x19
+###############################################################################
+# When disconnecting from Oberthur secure element, perform a warm-reset of
+# the secure element to deselect the applet.
+# The default hex value of the command is 0x3.  If this variable is undefined,
+# then this feature is not used.
+#OBERTHUR_WARM_RESET_COMMAND=0x03
+
+###############################################################################
+# Force UICC to only listen to the following technology(s).
+# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h.
+# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_B | NFA_TECHNOLOGY_MASK_F
+UICC_LISTEN_TECH_MASK=0x07
+
+###############################################################################
+# Forcing HOST to listen for a selected technology
+# 0x00 : Disable Host Listen
+# 0x01 : Enable Host Listen for Tech A
+# 0x02 : Enable Host Listen for Tech B
+# 0x03 : Enable Host Listen for Tech AB
+HOST_LISTEN_TECH_MASK=0x03
+
+###############################################################################
+# Enabling/Disabling Forward functionality
+# Disable           0x00
+# Enable            0x01
+NXP_FWD_FUNCTIONALITY_ENABLE=0x00
+
+###############################################################################
+# Allow UICC to be powered off if there is no traffic.
+# Timeout is in ms. If set to 0, then UICC will not be powered off.
+#UICC_IDLE_TIMEOUT=30000
+UICC_IDLE_TIMEOUT=0
+
+###############################################################################
+# AID for Empty Select command
+# If specified, this AID will be substituted when an Empty SELECT command is
+# detected.  The first byte is the length of the AID.  Maximum length is 16.
+AID_FOR_EMPTY_SELECT={08:A0:00:00:01:51:00:00:00}
+###############################################################################
+# Maximum Number of Credits to be allowed by the NFCC
+#   This value overrides what the NFCC specifices allowing the host to have
+#   the control to work-around transport limitations.  If this value does
+#   not exist or is set to 0, the NFCC will provide the number of credits.
+MAX_RF_DATA_CREDITS=1
+
+###############################################################################
+# This setting allows you to disable registering the T4t Virtual SE that causes
+# the NFCC to send PPSE requests to the DH.
+# The default setting is enabled (i.e. T4t Virtual SE is registered).
+#REGISTER_VIRTUAL_SE=1
+
+###############################################################################
+# When screen is turned off, specify the desired power state of the controller.
+# 0: power-off-sleep state; DEFAULT
+# 1: full-power state
+# 2: screen-off card-emulation (CE4/CE3/CE1 modes are used)
+SCREEN_OFF_POWER_STATE=1
+
+###############################################################################
+# Firmware patch file
+#  If the value is not set then patch download is disabled.
+#FW_PATCH="/vendor/firmware/bcm2079x_firmware.ncd"
+
+###############################################################################
+# Firmware pre-patch file (sent before the above patch file)
+#  If the value is not set then pre-patch is not used.
+#FW_PRE_PATCH="/vendor/firmware/bcm2079x_pre_firmware.ncd"
+
+###############################################################################
+# Firmware patch format
+#   1 = HCD
+#   2 = NCD (default)
+#NFA_CONFIG_FORMAT=2
+
+###############################################################################
+# SPD Debug mode
+#  If set to 1, any failure of downloading a patch will trigger a hard-stop
+#SPD_DEBUG=0
+
+###############################################################################
+# SPD Max Retry Count
+#  The number of attempts to download a patch before giving up (defualt is 3).
+#  Note, this resets after a power-cycle.
+#SPD_MAX_RETRY_COUNT=3
+
+###############################################################################
+# transport driver
+#
+# TRANSPORT_DRIVER=<driver>
+#
+#  where <driver> can be, for example:
+#    "/dev/ttyS"        (UART)
+#    "/dev/bcmi2cnfc"   (I2C)
+#    "hwtun"            (HW Tunnel)
+#    "/dev/bcmspinfc"   (SPI)
+#    "/dev/btusb0"      (BT USB)
+#TRANSPORT_DRIVER="/dev/bcm2079x-i2c"
+
+###############################################################################
+# power control driver
+# Specify a kernel driver that support ioctl commands to control NFC_EN and
+# NFC_WAKE gpio signals.
+#
+# POWER_CONTRL_DRIVER=<driver>
+#  where <driver> can be, for example:
+#    "/dev/nfcpower"
+#    "/dev/bcmi2cnfc"   (I2C)
+#    "/dev/bcmspinfc"   (SPI)
+#    i2c and spi driver may be used to control NFC_EN and NFC_WAKE signal
+#POWER_CONTROL_DRIVER="/dev/bcm2079x-i2c"
+
+###############################################################################
+# I2C transport driver options
+# Mako does not support 10-bit I2C addresses
+# Revert to 7-bit address
+#BCMI2CNFC_ADDRESS=0x77
+
+###############################################################################
+# I2C transport driver try to read multiple packets in read() if data is available
+# remove the comment below to enable this feature
+#READ_MULTIPLE_PACKETS=1
+
+###############################################################################
+# SPI transport driver options
+#SPI_NEGOTIATION={0A:F0:00:01:00:00:00:FF:FF:00:00}
+
+###############################################################################
+# UART transport driver options
+#
+# PORT=1,2,3,...
+# BAUD=115200, 19200, 9600, 4800,
+# DATABITS=8, 7, 6, 5
+# PARITY="even" | "odd" | "none"
+# STOPBITS="0" | "1" | "1.5" | "2"
+
+#UART_PORT=2
+#UART_BAUD=115200
+#UART_DATABITS=8
+#UART_PARITY="none"
+#UART_STOPBITS="1"
+
+###############################################################################
+# Insert a delay in microseconds per byte after a write to NFCC.
+# after writing a block of data to the NFCC, delay this an amopunt of time before
+# writing next block of data.  the delay is calculated as below
+#   NFC_WRITE_DELAY * (number of byte written) / 1000 milliseconds
+# e.g. after 259 bytes is written, delay (259 * 20 / 1000) 5 ms before next write
+#NFC_WRITE_DELAY=20
+
+###############################################################################
+# Maximum Number of Credits to be allowed by the NFCC
+#   This value overrides what the NFCC specifices allowing the host to have
+#   the control to work-around transport limitations.  If this value does
+#   not exist or is set to 0, the NFCC will provide the number of credits.
+MAX_RF_DATA_CREDITS=1
+
+###############################################################################
+# Default poll duration (in ms)
+#  The defualt is 500ms if not set (see nfc_target.h)
+#NFA_DM_DISC_DURATION_POLL=333
+###############################################################################
+# Antenna Configuration - This data is used when setting 0xC8 config item
+# at startup (before discovery is started).  If not used, no value is sent.
+#
+# The settings for this value are documented here:
+# http://wcgbu.broadcom.com/wpan/PM/Project%20Document%20Library/bcm20791B0/
+#   Design/Doc/PHY%20register%20settings/BCM20791-B2-1027-02_PHY_Recommended_Reg_Settings.xlsx
+# This document is maintained by Paul Forshaw.
+#
+# The values marked as ?? should be tweaked per antenna or customer/app:
+# {20:C8:1E:06:??:00:??:??:??:00:??:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:??:01:00:00:40:04}
+# array[0] = 0x20 is length of the payload from array[1] to the end
+# array[1] = 0xC8 is PREINIT_DSP_CFG
+#PREINIT_DSP_CFG={20:C8:1E:06:1F:00:0F:03:3C:00:04:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:48:01:00:00:40:04}
+
+
+###############################################################################
+# Choose the presence-check algorithm for type-4 tag.  If not defined, the default value is 1.
+# 0  NFA_RW_PRES_CHK_DEFAULT; Let stack selects an algorithm
+# 1  NFA_RW_PRES_CHK_I_BLOCK; ISO-DEP protocol's empty I-block
+# 2  NFA_RW_PRES_CHK_RESET; Deactivate to Sleep, then re-activate
+# 3  NFA_RW_PRES_CHK_RB_CH0; Type-4 tag protocol's ReadBinary command on channel 0
+# 4  NFA_RW_PRES_CHK_RB_CH3; Type-4 tag protocol's ReadBinary command on channel 3
+PRESENCE_CHECK_ALGORITHM=1
+
+###############################################################################
+# Force tag polling for the following technology(s).
+# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h.
+# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_B |
+#            NFA_TECHNOLOGY_MASK_F | NFA_TECHNOLOGY_MASK_ISO15693 |
+#            NFA_TECHNOLOGY_MASK_B_PRIME | NFA_TECHNOLOGY_MASK_KOVIO |
+#            NFA_TECHNOLOGY_MASK_A_ACTIVE | NFA_TECHNOLOGY_MASK_F_ACTIVE.
+#
+# Notable bits:
+# NFA_TECHNOLOGY_MASK_A             0x01    /* NFC Technology A             */
+# NFA_TECHNOLOGY_MASK_B             0x02    /* NFC Technology B             */
+# NFA_TECHNOLOGY_MASK_F             0x04    /* NFC Technology F             */
+# NFA_TECHNOLOGY_MASK_ISO15693	    0x08    /* Proprietary Technology       */
+# NFA_TECHNOLOGY_MASK_KOVIO	    0x20    /* Proprietary Technology       */
+# NFA_TECHNOLOGY_MASK_A_ACTIVE      0x40    /* NFC Technology A active mode */
+# NFA_TECHNOLOGY_MASK_F_ACTIVE      0x80    /* NFC Technology F active mode */
+POLLING_TECH_MASK=0xEF
+
+###############################################################################
+# Force P2P to only listen for the following technology(s).
+# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h.
+# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_F |
+#            NFA_TECHNOLOGY_MASK_A_ACTIVE | NFA_TECHNOLOGY_MASK_F_ACTIVE
+#
+# Notable bits:
+# NFA_TECHNOLOGY_MASK_A	            0x01    /* NFC Technology A             */
+# NFA_TECHNOLOGY_MASK_F	            0x04    /* NFC Technology F             */
+# NFA_TECHNOLOGY_MASK_A_ACTIVE      0x40    /* NFC Technology A active mode */
+# NFA_TECHNOLOGY_MASK_F_ACTIVE      0x80    /* NFC Technology F active mode */
+P2P_LISTEN_TECH_MASK=0xC4
+
+PRESERVE_STORAGE=0x01
+
+###############################################################################
+# Override the stack default for NFA_EE_MAX_EE_SUPPORTED set in nfc_target.h.
+# The value is set to 3 by default as it assumes we will discover 0xF2,
+# 0xF3, and 0xF4. If a platform will exclude and SE, this value can be reduced
+# so that the stack will not wait any longer than necessary.
+
+# Maximum EE supported number
+# NXP PN547C2 0x02
+# NXP PN65T 0x03
+# NXP PN548C2 0x02
+# NXP PN66T 0x03
+NFA_MAX_EE_SUPPORTED=0x02
+
+###############################################################################
+# NCI Hal Module name
+NCI_HAL_MODULE="nfc_nci.pn54x"
+
+##############################################################################
+# Deactivate notification wait time out in seconds used in ETSI Reader mode
+# 0 - Infinite wait
+NFA_DM_DISC_NTF_TIMEOUT=100
+
+###############################################################################
+# AID_MATCHING constants
+# AID_MATCHING_EXACT_ONLY 0x00
+# AID_MATCHING_EXACT_OR_PREFIX 0x01
+# AID_MATCHING_PREFIX_ONLY 0x02
+AID_MATCHING_MODE=0x01
+
+###############################################################################
+# Default Secure Element route id
+DEFAULT_OFFHOST_ROUTE=0x02
+
+###############################################################################
+# Vendor Specific Proprietary Protocol & Discovery Configuration
+# Set to 0xFF if unsupported
+#  byte[0] NCI_PROTOCOL_18092_ACTIVE
+#  byte[1] NCI_PROTOCOL_B_PRIME
+#  byte[2] NCI_PROTOCOL_DUAL
+#  byte[3] NCI_PROTOCOL_15693
+#  byte[4] NCI_PROTOCOL_KOVIO
+#  byte[5] NCI_PROTOCOL_MIFARE
+#  byte[6] NCI_DISCOVERY_TYPE_POLL_KOVIO
+#  byte[7] NCI_DISCOVERY_TYPE_POLL_B_PRIME
+#  byte[8] NCI_DISCOVERY_TYPE_LISTEN_B_PRIME
+NFA_PROPRIETARY_CFG={05:FF:FF:06:81:80:70:FF:FF}
+
+#################################################################################
+# Bail out mode
+#  If set to 1, NFCC is using bail out mode for either Type A or Type B poll.
+NFA_POLL_BAIL_OUT_MODE=0x01
+#################################################################################
--- a/nfc/libnfc-nci-hi6250-pra.conf
+++ b/nfc/libnfc-nci-hi6250-pra.conf
@ -0,0 +1,395 @@
+###################### Start of libnfc-nci.conf #######################
+###################### Huawei P8 lite 2017 version  ###################
+
+###############################################################################
+# Application options
+NFC_DEBUG_ENABLED=0
+APPL_TRACE_LEVEL=0x02
+PROTOCOL_TRACE_LEVEL=0xFFFFFFFF
+
+###############################################################################
+# performance measurement
+# Change this setting to control how often USERIAL log the performance (throughput)
+# data on read/write/poll
+# defailt is to log performance dara for every 100 read or write
+#REPORT_PERFORMANCE_MEASURE=100
+
+###############################################################################
+# File used for NFA storage
+NFA_STORAGE="/data/nfc"
+
+###############################################################################
+# Snooze Mode Settings
+#
+#  By default snooze mode is enabled.  Set SNOOZE_MODE_CFG byte[0] to 0
+#  to disable.
+#
+#  If SNOOZE_MODE_CFG is not provided, the default settings are used:
+#  They are as follows:
+#       8             Sleep Mode (0=Disabled 1=UART 8=SPI/I2C)
+#       0             Idle Threshold Host
+#       0             Idle Threshold HC
+#       0             NFC Wake active mode (0=ActiveLow 1=ActiveHigh)
+#       1             Host Wake active mode (0=ActiveLow 1=ActiveHigh)
+#
+#SNOOZE_MODE_CFG={08:00:00:00:01}
+
+###############################################################################
+# Insert a delay in milliseconds after NFC_WAKE and before write to NFCC
+#NFC_WAKE_DELAY=20
+
+###############################################################################
+# Various Delay settings (in ms) used in USERIAL
+#  POWER_ON_DELAY
+#    Delay after turning on chip, before writing to transport (default 300)
+#  PRE_POWER_OFF_DELAY
+#    Delay after deasserting NFC-Wake before turn off chip (default 0)
+#  POST_POWER_OFF_DELAY
+#    Delay after turning off chip, before USERIAL_close returns (default 0)
+#
+#POWER_ON_DELAY=300
+#PRE_POWER_OFF_DELAY=0
+#POST_POWER_OFF_DELAY=0
+
+###############################################################################
+# Maximum time (ms) to wait for RESET NTF after setting REG_PU to high
+# The default is 1000.
+#NFCC_ENABLE_TIMEOUT=0
+
+###############################################################################
+# LPTD mode configuration
+#  byte[0] is the length of the remaining bytes in this value
+#     if set to 0, LPTD params will NOT be sent to NFCC (i.e. disabled).
+#  byte[1] is the param id it should be set to B9.
+#  byte[2] is the length of the LPTD parameters
+#  byte[3] indicates if LPTD is enabled
+#     if set to 0, LPTD will be disabled (parameters will still be sent).
+#  byte[4-n] are the LPTD parameters.
+#  By default, LPTD is enabled and default settings are used.
+#  See nfc_hal_dm_cfg.c for defaults
+#LPTD_CFG={23:B9:21:01:02:FF:FF:04:A0:0F:40:00:80:02:02:10:00:00:00:31:0C:30:00:00:00:00:00:00:00:00:00:00:00:00:00:00}
+
+###############################################################################
+# Startup Configuration (100 bytes maximum)
+#
+# For the 0xCA parameter, byte[9] (marked by 'AA') is for UICC0, and byte[10] (marked by BB) is
+#    for UICC1.  The values are defined as:
+#   0 : UICCx only supports ISO_DEP in low power mode.
+#   2 : UICCx only supports Mifare in low power mode.
+#   3 : UICCx supports both ISO_DEP and Mifare in low power mode.
+#
+#                                                                          AA BB
+#NFA_DM_START_UP_CFG={1F:CB:01:01:A5:01:01:CA:14:00:00:00:00:06:E8:03:00:00:00:00:00:00:00:00:00:00:00:00:00:80:01:01}
+
+###############################################################################
+# Startup Vendor Specific Configuration (100 bytes maximum);
+#  byte[0] TLV total len = 0x5
+#  byte[1] NCI_MTS_CMD|NCI_GID_PROP = 0x2f
+#  byte[2] NCI_MSG_FRAME_LOG = 0x9
+#  byte[3] 2
+#  byte[4] 0=turn off RF frame logging; 1=turn on
+#  byte[5] 0=turn off SWP frame logging; 1=turn on
+#  NFA_DM_START_UP_VSC_CFG={05:2F:09:02:01:01}
+
+###############################################################################
+# Antenna Configuration - This data is used when setting 0xC8 config item
+# at startup (before discovery is started).  If not used, no value is sent.
+#
+# The settings for this value are documented here:
+# http://wcgbu.broadcom.com/wpan/PM/Project%20Document%20Library/bcm20791B0/
+#   Design/Doc/PHY%20register%20settings/BCM20791-B2-1027-02_PHY_Recommended_Reg_Settings.xlsx
+# This document is maintained by Paul Forshaw.
+#
+# The values marked as ?? should be tweaked per antenna or customer/app:
+# {20:C8:1E:06:??:00:??:??:??:00:??:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:??:01:00:00:40:04}
+# array[0] = 0x20 is length of the payload from array[1] to the end
+# array[1] = 0xC8 is PREINIT_DSP_CFG
+#PREINIT_DSP_CFG={20:C8:1E:06:1F:00:0F:03:3C:00:04:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:48:01:00:00:40:04}
+
+###############################################################################
+# Configure crystal frequency when internal LPO can't detect the frequency.
+#XTAL_FREQUENCY=0
+###############################################################################
+# Configure the default Destination Gate used by HCI (the default is 4, which
+# is the ETSI loopback gate.
+NFA_HCI_DEFAULT_DEST_GATE=0xF0
+
+###############################################################################
+# Configure the single default SE to use.  The default is to use the first
+# SE that is detected by the stack.  This value might be used when the phone
+# supports multiple SE (e.g. 0xF3 and 0xF4) but you want to force it to use
+# one of them (e.g. 0xF4).
+#ACTIVE_SE=0xF3
+
+###############################################################################
+# Configure the default NfcA/IsoDep techology and protocol route. Can be
+# either a secure element (e.g. 0xF4) or the host (0x00)
+#DEFAULT_ISODEP_ROUTE=0x00
+
+###############################################################################
+# Configure the NFC Extras to open and use a static pipe.  If the value is
+# not set or set to 0, then the default is use a dynamic pipe based on a
+# destination gate (see NFA_HCI_DEFAULT_DEST_GATE).  Note there is a value
+# for each UICC (where F3="UICC0" and F4="UICC1")
+#NFA_HCI_STATIC_PIPE_ID_F3=0x70
+#NFA_HCI_STATIC_PIPE_ID_01=0x19
+NFA_HCI_STATIC_PIPE_ID_C0=0x19
+NFA_HCI_STATIC_PIPE_ID_02=0x20
+###############################################################################
+# When disconnecting from Oberthur secure element, perform a warm-reset of
+# the secure element to deselect the applet.
+# The default hex value of the command is 0x3.  If this variable is undefined,
+# then this feature is not used.
+#OBERTHUR_WARM_RESET_COMMAND=0x03
+
+###############################################################################
+# Force UICC to only listen to the following technology(s).
+# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h.
+# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_B | NFA_TECHNOLOGY_MASK_F
+UICC_LISTEN_TECH_MASK=0x07
+
+###############################################################################
+# Forcing HOST to listen for a selected protocol
+# 0x00 : Disable Host Listen
+# 0x01 : Enable Host to Listen (A)  for ISO-DEP tech A
+# 0x02 : Enable Host to Listen (B)  for ISO-DEP tech B
+# 0x04 : Enable Host to Listen (F)  for T3T Tag Type Protocol tech F
+# 0x07 : Enable Host to Listen (ABF)for ISO-DEP tech AB & T3T Tag Type Protocol tech F
+HOST_LISTEN_TECH_MASK=0x07
+
+###############################################################################
+# Enabling/Disabling Forward functionality
+# Disable           0x00
+# Enable            0x01
+NXP_FWD_FUNCTIONALITY_ENABLE=0x00
+
+###############################################################################
+# Allow UICC to be powered off if there is no traffic.
+# Timeout is in ms. If set to 0, then UICC will not be powered off.
+#UICC_IDLE_TIMEOUT=30000
+UICC_IDLE_TIMEOUT=0
+
+###############################################################################
+# AID for Empty Select command
+# If specified, this AID will be substituted when an Empty SELECT command is
+# detected.  The first byte is the length of the AID.  Maximum length is 16.
+AID_FOR_EMPTY_SELECT={08:A0:00:00:01:51:00:00:00}
+###############################################################################
+# Maximum Number of Credits to be allowed by the NFCC
+#   This value overrides what the NFCC specifices allowing the host to have
+#   the control to work-around transport limitations.  If this value does
+#   not exist or is set to 0, the NFCC will provide the number of credits.
+MAX_RF_DATA_CREDITS=1
+
+###############################################################################
+# This setting allows you to disable registering the T4t Virtual SE that causes
+# the NFCC to send PPSE requests to the DH.
+# The default setting is enabled (i.e. T4t Virtual SE is registered).
+#REGISTER_VIRTUAL_SE=1
+
+###############################################################################
+# When screen is turned off, specify the desired power state of the controller.
+# 0: power-off-sleep state; DEFAULT
+# 1: full-power state
+# 2: screen-off card-emulation (CE4/CE3/CE1 modes are used)
+SCREEN_OFF_POWER_STATE=1
+
+###############################################################################
+# Firmware patch file
+#  If the value is not set then patch download is disabled.
+#FW_PATCH="/vendor/firmware/bcm2079x_firmware.ncd"
+
+###############################################################################
+# Firmware pre-patch file (sent before the above patch file)
+#  If the value is not set then pre-patch is not used.
+#FW_PRE_PATCH="/vendor/firmware/bcm2079x_pre_firmware.ncd"
+
+###############################################################################
+# Firmware patch format
+#   1 = HCD
+#   2 = NCD (default)
+#NFA_CONFIG_FORMAT=2
+
+###############################################################################
+# SPD Debug mode
+#  If set to 1, any failure of downloading a patch will trigger a hard-stop
+#SPD_DEBUG=0
+
+###############################################################################
+# SPD Max Retry Count
+#  The number of attempts to download a patch before giving up (defualt is 3).
+#  Note, this resets after a power-cycle.
+#SPD_MAX_RETRY_COUNT=3
+
+###############################################################################
+# transport driver
+#
+# TRANSPORT_DRIVER=<driver>
+#
+#  where <driver> can be, for example:
+#    "/dev/ttyS"        (UART)
+#    "/dev/bcmi2cnfc"   (I2C)
+#    "hwtun"            (HW Tunnel)
+#    "/dev/bcmspinfc"   (SPI)
+#    "/dev/btusb0"      (BT USB)
+#TRANSPORT_DRIVER="/dev/bcm2079x-i2c"
+
+###############################################################################
+# power control driver
+# Specify a kernel driver that support ioctl commands to control NFC_EN and
+# NFC_WAKE gpio signals.
+#
+# POWER_CONTRL_DRIVER=<driver>
+#  where <driver> can be, for example:
+#    "/dev/nfcpower"
+#    "/dev/bcmi2cnfc"   (I2C)
+#    "/dev/bcmspinfc"   (SPI)
+#    i2c and spi driver may be used to control NFC_EN and NFC_WAKE signal
+#POWER_CONTROL_DRIVER="/dev/bcm2079x-i2c"
+
+###############################################################################
+# I2C transport driver options
+# Mako does not support 10-bit I2C addresses
+# Revert to 7-bit address
+#BCMI2CNFC_ADDRESS=0x77
+
+###############################################################################
+# I2C transport driver try to read multiple packets in read() if data is available
+# remove the comment below to enable this feature
+#READ_MULTIPLE_PACKETS=1
+
+###############################################################################
+# SPI transport driver options
+#SPI_NEGOTIATION={0A:F0:00:01:00:00:00:FF:FF:00:00}
+
+###############################################################################
+# UART transport driver options
+#
+# PORT=1,2,3,...
+# BAUD=115200, 19200, 9600, 4800,
+# DATABITS=8, 7, 6, 5
+# PARITY="even" | "odd" | "none"
+# STOPBITS="0" | "1" | "1.5" | "2"
+
+#UART_PORT=2
+#UART_BAUD=115200
+#UART_DATABITS=8
+#UART_PARITY="none"
+#UART_STOPBITS="1"
+
+###############################################################################
+# Insert a delay in microseconds per byte after a write to NFCC.
+# after writing a block of data to the NFCC, delay this an amopunt of time before
+# writing next block of data.  the delay is calculated as below
+#   NFC_WRITE_DELAY * (number of byte written) / 1000 milliseconds
+# e.g. after 259 bytes is written, delay (259 * 20 / 1000) 5 ms before next write
+#NFC_WRITE_DELAY=20
+
+###############################################################################
+# Maximum Number of Credits to be allowed by the NFCC
+#   This value overrides what the NFCC specifices allowing the host to have
+#   the control to work-around transport limitations.  If this value does
+#   not exist or is set to 0, the NFCC will provide the number of credits.
+#MAX_RF_DATA_CREDITS=1
+
+###############################################################################
+# Default poll duration (in ms)
+#  The defualt is 500ms if not set (see nfc_target.h)
+#NFA_DM_DISC_DURATION_POLL=333
+###############################################################################
+# Antenna Configuration - This data is used when setting 0xC8 config item
+# at startup (before discovery is started).  If not used, no value is sent.
+#
+# The settings for this value are documented here:
+# http://wcgbu.broadcom.com/wpan/PM/Project%20Document%20Library/bcm20791B0/
+#   Design/Doc/PHY%20register%20settings/BCM20791-B2-1027-02_PHY_Recommended_Reg_Settings.xlsx
+# This document is maintained by Paul Forshaw.
+#
+# The values marked as ?? should be tweaked per antenna or customer/app:
+# {20:C8:1E:06:??:00:??:??:??:00:??:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:??:01:00:00:40:04}
+# array[0] = 0x20 is length of the payload from array[1] to the end
+# array[1] = 0xC8 is PREINIT_DSP_CFG
+#PREINIT_DSP_CFG={20:C8:1E:06:1F:00:0F:03:3C:00:04:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:48:01:00:00:40:04}
+
+
+###############################################################################
+# Choose the presence-check algorithm for type-4 tag.  If not defined, the default value is 1.
+# 0  NFA_RW_PRES_CHK_DEFAULT; Let stack selects an algorithm
+# 1  NFA_RW_PRES_CHK_I_BLOCK; ISO-DEP protocol's empty I-block
+# 2  NFA_RW_PRES_CHK_RESET; Deactivate to Sleep, then re-activate
+# 3  NFA_RW_PRES_CHK_RB_CH0; Type-4 tag protocol's ReadBinary command on channel 0
+# 4  NFA_RW_PRES_CHK_RB_CH3; Type-4 tag protocol's ReadBinary command on channel 3
+#PRESENCE_CHECK_ALGORITHM=0
+
+###############################################################################
+# Force tag polling for the following technology(s).
+# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h.
+# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_B |
+#            NFA_TECHNOLOGY_MASK_F | NFA_TECHNOLOGY_MASK_ISO15693 |
+#            NFA_TECHNOLOGY_MASK_B_PRIME | NFA_TECHNOLOGY_MASK_KOVIO |
+#            NFA_TECHNOLOGY_MASK_A_ACTIVE | NFA_TECHNOLOGY_MASK_F_ACTIVE.
+#
+# Notable bits:
+# NFA_TECHNOLOGY_MASK_A             0x01    /* NFC Technology A             */
+# NFA_TECHNOLOGY_MASK_B             0x02    /* NFC Technology B             */
+# NFA_TECHNOLOGY_MASK_F             0x04    /* NFC Technology F             */
+# NFA_TECHNOLOGY_MASK_ISO15693	    0x08    /* Proprietary Technology       */
+# NFA_TECHNOLOGY_MASK_KOVIO	    0x20    /* Proprietary Technology       */
+# NFA_TECHNOLOGY_MASK_A_ACTIVE      0x40    /* NFC Technology A active mode */
+# NFA_TECHNOLOGY_MASK_F_ACTIVE      0x80    /* NFC Technology F active mode */
+POLLING_TECH_MASK=0xEF
+
+###############################################################################
+# Force P2P to only listen for the following technology(s).
+# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h.
+# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_F |
+#            NFA_TECHNOLOGY_MASK_A_ACTIVE | NFA_TECHNOLOGY_MASK_F_ACTIVE
+#
+# Notable bits:
+# NFA_TECHNOLOGY_MASK_A	            0x01    /* NFC Technology A             */
+# NFA_TECHNOLOGY_MASK_F	            0x04    /* NFC Technology F             */
+# NFA_TECHNOLOGY_MASK_A_ACTIVE      0x40    /* NFC Technology A active mode */
+# NFA_TECHNOLOGY_MASK_F_ACTIVE      0x80    /* NFC Technology F active mode */
+P2P_LISTEN_TECH_MASK=0xC4
+
+PRESERVE_STORAGE=0x01
+
+###############################################################################
+# NCI Hal Module name
+NCI_HAL_MODULE="nfc_nci.pn54x"
+
+##############################################################################
+# Deactivate notification wait time out in seconds used in ETSI Reader mode
+# 0 - Infinite wait
+NFA_DM_DISC_NTF_TIMEOUT=100
+
+###############################################################################
+# AID_MATCHING constants
+# AID_MATCHING_EXACT_ONLY 0x00
+# AID_MATCHING_EXACT_OR_PREFIX 0x01
+# AID_MATCHING_PREFIX_ONLY 0x02
+AID_MATCHING_MODE=0x01
+
+###############################################################################
+# Default Secure Element route id
+DEFAULT_OFFHOST_ROUTE=0x02
+
+###############################################################################
+# Vendor Specific Proprietary Protocol & Discovery Configuration
+# Set to 0xFF if unsupported
+#  byte[0] NCI_PROTOCOL_18092_ACTIVE
+#  byte[1] NCI_PROTOCOL_B_PRIME
+#  byte[2] NCI_PROTOCOL_DUAL
+#  byte[3] NCI_PROTOCOL_15693
+#  byte[4] NCI_PROTOCOL_KOVIO
+#  byte[5] NCI_PROTOCOL_MIFARE
+#  byte[6] NCI_DISCOVERY_TYPE_POLL_KOVIO
+#  byte[7] NCI_DISCOVERY_TYPE_POLL_B_PRIME
+#  byte[8] NCI_DISCOVERY_TYPE_LISTEN_B_PRIME
+NFA_PROPRIETARY_CFG={05:FF:FF:06:81:80:70:FF:FF}
+
+#################################################################################
+# Bail out mode
+#  If set to 1, NFCC is using bail out mode for either Type A or Type B poll.
+NFA_POLL_BAIL_OUT_MODE=0x01
+#################################################################################
--- a/nfc/libnfc-nci-huawei.conf
+++ b/nfc/libnfc-nci-huawei.conf
--- a/nfc/libnfc-nci.conf
+++ b/nfc/libnfc-nci.conf
--- a/nfc/libnfc-nxp-hi6250-pra.conf
+++ b/nfc/libnfc-nxp-hi6250-pra.conf
@ -0,0 +1,705 @@
+## This file is used by NFC NXP NCI HAL(external/libnfc-nci/halimpl/pn551)
+## and NFC Service Java Native Interface Extensions (packages/apps/Nfc/nci/jni/extns/pn551)
+
+###############################################################################
+# Application options
+# Logging Levels
+# NXPLOG_DEFAULT_LOGLEVEL    0x01
+# ANDROID_LOG_DEBUG          0x03
+# ANDROID_LOG_WARN           0x02
+# ANDROID_LOG_ERROR          0x01
+# ANDROID_LOG_SILENT         0x00
+#
+NXPLOG_EXTNS_LOGLEVEL=0x03
+NXPLOG_NCIHAL_LOGLEVEL=0x03
+NXPLOG_NCIX_LOGLEVEL=0x03
+NXPLOG_NCIR_LOGLEVEL=0x03
+NXPLOG_FWDNLD_LOGLEVEL=0x03
+NXPLOG_TML_LOGLEVEL=0x03
+
+###############################################################################
+# Nfc Device Node name
+NXP_NFC_DEV_NODE="/dev/pn544"
+
+###############################################################################
+# Extension for Mifare reader enable
+MIFARE_READER_ENABLE=0x01
+
+###############################################################################
+# Vzw Feature enable
+VZW_FEATURE_ENABLE=0x01
+
+###############################################################################
+# File name for Firmware
+NXP_FW_NAME="libpn551_fw_10_05_03_64bits.so"
+
+###############################################################################
+# System clock source selection configuration
+#define CLK_SRC_XTAL       1
+#define CLK_SRC_PLL        2
+
+NXP_SYS_CLK_SRC_SEL=0x02
+
+###############################################################################
+# System clock frequency selection configuration
+#define CLK_FREQ_13MHZ         1
+#define CLK_FREQ_19_2MHZ       2
+#define CLK_FREQ_24MHZ         3
+#define CLK_FREQ_26MHZ         4
+#define CLK_FREQ_38_4MHZ       5
+#define CLK_FREQ_52MHZ         6
+
+NXP_SYS_CLK_FREQ_SEL=0x02
+
+###############################################################################
+# The timeout value to be used for clock request acknowledgment
+# min value = 0x01 to max = 0x06
+
+NXP_SYS_CLOCK_TO_CFG=0x06
+
+###############################################################################
+# NXP proprietary settings
+NXP_ACT_PROP_EXTN={2F, 02, 00}
+
+###############################################################################
+# NFC forum profile settings
+NXP_NFC_PROFILE_EXTN={20, 02, 05, 01, A0, 44, 01, 00}
+
+###############################################################################
+# NFCC Configuration Control
+# Allow NFCC to manage RF Config       0x01
+# Don't allow NFCC to manage RF Config 0x00
+NXP_NFC_MERGE_RF_PARAMS={20, 02, 04, 01, 85, 01, 01}
+
+###############################################################################
+# Standby enable settings
+NXP_CORE_STANDBY={2F, 00, 01, 01}
+
+###############################################################################
+# NXP TVDD configurations settings
+# Allow NFCC to configure External TVDD, There are currently three
+#configurations (1, 2 and 3) are supported, out of them only one can be
+#supported.
+
+NXP_EXT_TVDD_CFG=0x02
+
+#config1:SLALM, 3.3V for both RM and CM
+NXP_EXT_TVDD_CFG_1={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 02, 09, 00}
+
+#config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM,
+#monitoring 5V from DCDC, 3.3V for both RM and CM, DCDCWaitTime=4.2ms
+#NXP_EXT_TVDD_CFG_2={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 56, 24, 08 }
+NXP_EXT_TVDD_CFG_2={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 56, 4C, 01}
+
+#config3: use DCDC in CE, use Tx_Pwr_Req, SLALM, monitoring 5V from DCDC,
+#DCDCWaitTime=4.2ms
+NXP_EXT_TVDD_CFG_3={20, 02, 0B, 02, A0, 66, 01, 01, A0, 0E, 03, 52, 40, 0A}
+
+###############################################################################
+# NXP RF ALMSL configuration settings for FW VERSION = 10.05.03
+#
+#    A0, 0D, 03, 00, 40, 01                RF_CLIF_CFG_BOOT            CLIF_ANA_NFCLD_REG
+#    A0, 0D, 06, 00, FF, 05, 04, 06, 00    RF_CLIF_CFG_BOOT            SMU_PMU_REG (0x40024010)
+#    A0, 0D, 06, 00, 35, FF, 01, FF, 02    RF_CLIF_CFG_BOOT            CLIF_AGC_INPUT_REG
+#    A0, 0D, 06, 00, 33, 07, 40, 00, 00    RF_CLIF_CFG_BOOT            CLIF_AGC_CONFIG0_REG
+#    A0, 0D, 03, 02, 40, 00                RF_CLIF_CFG_IDLE            CLIF_ANA_NFCLD_REG
+#    A0, 0D, 03, 04, 43, 20                RF_CLIF_CFG_INITIATOR       CLIF_ANA_PBF_CONTROL_REG
+#    A0, 0D, 03, 04, 47, 02                RF_CLIF_CFG_INITIATOR       CLIF_ANA_AGC_REG
+#    A0, 0D, 06, 04, 35, F4, 01, F4, 01    RF_CLIF_CFG_INITIATOR       CLIF_AGC_INPUT_REG
+#    A0, 0D, 06, 04, FF, 05, 00, 00, 00    RF_CLIF_CFG_INITIATOR       SMU_PMU_REG (0x40024010)
+#    A0, 0D, 06, 05, 45, 80, 40, 00, 00    RF_CLIF_CFG_INITIATOR       CLIF_ANA_CM_CONFIG_REG
+#    A0, 0D, 06, 05, 35, FF, 01, FF, 02    RF_CLIF_CFG_INITIATOR       CLIF_AGC_INPUT_REG
+#    A0, 0D, 06, 05, 33, 07, 40, 00, 00    RF_CLIF_CFG_INITIATOR       CLIF_AGC_CONFIG0_REG
+#    A0, 0D, 06, 06, 44, A3, 90, 03, 00    RF_CLIF_CFG_TARGET          CLIF_ANA_RX_REG
+#    A0, 0D, 03, 06, 47, 02                RF_CLIF_CFG_TARGET          CLIF_ANA_AGC_REG
+#    A0, 0D, 06, 06, 35, FF, 03, FF, 03    RF_CLIF_CFG_TARGET          CLIF_AGC_INPUT_REG
+#    A0, 0D, 06, 06, 34, F7, 7F, 00, 10    RF_CLIF_CFG_TARGET          CLIF_AGC_CONFIG1_REG
+#    A0, 0D, 06, 06, 33, 03, 40, 00, 00    RF_CLIF_CFG_TARGET          CLIF_AGC_CONFIG0_REG
+#    A0, 0D, 06, 06, 30, C8, 00, 64, 00    RF_CLIF_CFG_TARGET          CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+#    A0, 0D, 06, 06, 2F, AF, 05, 80, 17    RF_CLIF_CFG_TARGET          CLIF_SIGPRO_ADCBCM_CONFIG_REG
+#    A0, 0D, 06, 06, 03, 00, 6D, 00, 20    RF_CLIF_CFG_TARGET          CLIF_TRANSCEIVE_CONTROL_REG
+#    A0, 0D, 03, 06, 43, 20                RF_CLIF_CFG_TARGET          CLIF_ANA_PBF_CONTROL_REG
+#    A0, 0D, 06, 06, 42, 00, 02, FF, FF    RF_CLIF_CFG_TARGET          CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 03, 06, 41, 40                RF_CLIF_CFG_TARGET          CLIF_ANA_TX_CLK_CONTROL_REG
+#    A0, 0D, 03, 06, 37, 08                RF_CLIF_CFG_TARGET          CLIF_TX_CONTROL_REG
+#    A0, 0D, 03, 06, 16, 00                RF_CLIF_CFG_TARGET          CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 06, 15, 00                RF_CLIF_CFG_TARGET          CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 06, 3F, 04                RF_CLIF_CFG_TARGET          CLIF_TEST_CONTROL_REG
+#    A0, 0D, 03, 06, 80, 03                RF_CLIF_CFG_TARGET          CLIF_SPARE_REG
+#    A0, 0D, 06, 06, FF, 05, 00, 00, 00    RF_CLIF_CFG_TARGET          SMU_PMU_REG (0x40024010)
+#    A0, 0D, 03, 07, 3F, 00                RF_CLIF_CFG_TARGET          CLIF_TEST_CONTROL_REG
+#    A0, 0D, 06, 07, 35, FF, 01, FF, 02    RF_CLIF_CFG_TARGET          CLIF_AGC_INPUT_REG
+#    A0, 0D, 06, 07, 33, 07, 40, 00, 00    RF_CLIF_CFG_TARGET          CLIF_AGC_CONFIG0_REG
+#    A0, 0D, 06, 18, 34, 00, 00, E1, 03    RF_CLIF_CFG_TECHNO_I_RXB    CLIF_AGC_CONFIG1_REG
+#    A0, 0D, 06, 18, 33, 0F, 83, 00, 00    RF_CLIF_CFG_TECHNO_I_RXB    CLIF_AGC_CONFIG0_REG
+#    A0, 0D, 06, 1C, 34, 00, 00, E1, 03    RF_CLIF_CFG_TECHNO_I_RXF_P  CLIF_AGC_CONFIG1_REG
+#    A0, 0D, 06, 1C, 33, 0F, 83, 00, 00    RF_CLIF_CFG_TECHNO_I_RXF_P  CLIF_AGC_CONFIG0_REG
+#    A0, 0D, 06, 20, 4A, 00, 00, 00, 00    RF_CLIF_CFG_TECHNO_I_TX15693CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 06, 20, 42, 88, 10, FF, FF    RF_CLIF_CFG_TECHNO_I_TX15693CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 03, 20, 16, 00                RF_CLIF_CFG_TECHNO_I_TX15693CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 20, 15, 00                RF_CLIF_CFG_TECHNO_I_TX15693CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 04, 22, 44, 22, 00            RF_CLIF_CFG_TECHNO_I_RX15693CLIF_ANA_RX_REG
+#    A0, 0D, 06, 22, 2D, 50, 44, 0C, 00    RF_CLIF_CFG_TECHNO_I_RX15693CLIF_SIGPRO_RM_CONFIG1_REG
+#    A0, 0D, 04, 32, 03, 40, 3D            RF_CLIF_CFG_BR_106_I_TXA    CLIF_TRANSCEIVE_CONTROL_REG
+#    A0, 0D, 06, 32, 42, F8, 10, FF, FF    RF_CLIF_CFG_BR_106_I_TXA    CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 03, 32, 16, 00                RF_CLIF_CFG_BR_106_I_TXA    CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 32, 15, 01                RF_CLIF_CFG_BR_106_I_TXA    CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 32, 0D, 22                RF_CLIF_CFG_BR_106_I_TXA    CLIF_TX_DATA_MOD_REG
+#    A0, 0D, 03, 32, 14, 22                RF_CLIF_CFG_BR_106_I_TXA    CLIF_TX_SYMBOL23_MOD_REG
+#    A0, 0D, 06, 32, 4A, 33, 07, 00, 08    RF_CLIF_CFG_BR_106_I_TXA    CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 06, 34, 2D, 24, 47, 0C, 00    RF_CLIF_CFG_BR_106_I_RXA_P  CLIF_SIGPRO_RM_CONFIG1_REG
+#    A0, 0D, 06, 34, 34, 00, 00, EC, 03    RF_CLIF_CFG_BR_106_I_RXA_P  CLIF_AGC_CONFIG1_REG
+#    A0, 0D, 06, 34, 33, 0F, 01, 01, 70    RF_CLIF_CFG_BR_106_I_RXA_P  CLIF_AGC_CONFIG0_REG
+#    A0, 0D, 04, 34, 44, 21, 00            RF_CLIF_CFG_BR_106_I_RXA_P  CLIF_ANA_RX_REG
+#    A0, 0D, 06, 38, 4A, 33, 07, 00, 08    RF_CLIF_CFG_BR_212_I_TXA    CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 06, 38, 42, 68, 10, FF, FF    RF_CLIF_CFG_BR_212_I_TXA    CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 03, 38, 16, 00                RF_CLIF_CFG_BR_212_I_TXA    CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 38, 15, 00                RF_CLIF_CFG_BR_212_I_TXA    CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 04, 3A, 44, 26, 00            RF_CLIF_CFG_BR_212_I_RXA    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 3A, 2D, 15, 47, 0D, 00    RF_CLIF_CFG_BR_212_I_RXA    CLIF_SIGPRO_RM_CONFIG1_REG
+#    A0, 0D, 06, 3A, 34, 00, 00, E1, 03    RF_CLIF_CFG_BR_212_I_RXA    CLIF_AGC_CONFIG1_REG
+#    A0, 0D, 06, 3A, 33, 0B, 83, 00, 00    RF_CLIF_CFG_BR_212_I_RXA    CLIF_AGC_CONFIG0_REG
+#    A0, 0D, 06, 3C, 4A, 52, 07, 00, 1B    RF_CLIF_CFG_BR_424_I_TXA    CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 06, 3C, 42, 68, 10, FF, FF    RF_CLIF_CFG_BR_424_I_TXA    CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 03, 3C, 16, 00                RF_CLIF_CFG_BR_424_I_TXA    CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 3C, 15, 00                RF_CLIF_CFG_BR_424_I_TXA    CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 04, 3E, 44, 26, 00            RF_CLIF_CFG_BR_424_I_RXA    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 3E, 2D, 15, 47, 0D, 00    RF_CLIF_CFG_BR_424_I_RXA    CLIF_SIGPRO_RM_CONFIG1_REG
+#    A0, 0D, 06, 3E, 34, 00, 00, E1, 03    RF_CLIF_CFG_BR_424_I_RXA    CLIF_AGC_CONFIG1_REG
+#    A0, 0D, 06, 3E, 33, 0B, 83, 00, 00    RF_CLIF_CFG_BR_424_I_RXA    CLIF_AGC_CONFIG0_REG
+#    A0, 0D, 06, 40, 42, F0, 10, FF, FF    RF_CLIF_CFG_BR_848_I_TXA    CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 03, 40, 0D, 02                RF_CLIF_CFG_BR_848_I_TXA    CLIF_TX_DATA_MOD_REG
+#    A0, 0D, 03, 40, 14, 02                RF_CLIF_CFG_BR_848_I_TXA    CLIF_TX_SYMBOL23_MOD_REG
+#    A0, 0D, 06, 40, 4A, 12, 07, 00, 00    RF_CLIF_CFG_BR_848_I_TXA    CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 03, 40, 16, 00                RF_CLIF_CFG_BR_848_I_TXA    CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 40, 15, 00                RF_CLIF_CFG_BR_848_I_TXA    CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 04, 42, 44, 26, 00            RF_CLIF_CFG_BR_848_I_RXA    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 42, 2D, 15, 47, 0D, 00    RF_CLIF_CFG_BR_848_I_RXA    CLIF_SIGPRO_RM_CONFIG1_REG
+#    A0, 0D, 06, 42, 34, 00, 00, E1, 03    RF_CLIF_CFG_BR_848_I_RXA    CLIF_AGC_CONFIG1_REG
+#    A0, 0D, 06, 42, 33, 0B, 83, 00, 00    RF_CLIF_CFG_BR_848_I_RXA    CLIF_AGC_CONFIG0_REG
+#    A0, 0D, 04, 46, 44, 26, 00            RF_CLIF_CFG_BR_106_I_RXB    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 46, 2D, 15, 25, 0D, 00    RF_CLIF_CFG_BR_106_I_RXB    CLIF_SIGPRO_RM_CONFIG1_REG
+#    A0, 0D, 06, 44, 4A, 21, 07, 00, 07    RF_CLIF_CFG_BR_106_I_TXB    CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 06, 44, 42, 88, 10, FF, FF    RF_CLIF_CFG_BR_106_I_TXB    CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 03, 44, 16, 00                RF_CLIF_CFG_BR_106_I_TXB    CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 44, 15, 00                RF_CLIF_CFG_BR_106_I_TXB    CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 04, 4A, 44, 21, 00            RF_CLIF_CFG_BR_212_I_RXB    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 4A, 2D, 15, 9D, 0D, 00    RF_CLIF_CFG_BR_212_I_RXB    CLIF_SIGPRO_RM_CONFIG1_REG
+#    A0, 0D, 06, 48, 4A, 21, 07, 00, 07    RF_CLIF_CFG_BR_212_I_TXB    CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 06, 48, 42, 88, 10, FF, FF    RF_CLIF_CFG_BR_212_I_TXB    CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 03, 48, 16, 00                RF_CLIF_CFG_BR_212_I_TXB    CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 48, 15, 00                RF_CLIF_CFG_BR_212_I_TXB    CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 04, 4E, 44, 26, 00            RF_CLIF_CFG_BR_424_I_RXB    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 4E, 2D, 15, 25, 0D, 00    RF_CLIF_CFG_BR_424_I_RXB    CLIF_SIGPRO_RM_CONFIG1_REG
+#    A0, 0D, 06, 4C, 4A, 21, 07, 00, 07    RF_CLIF_CFG_BR_424_I_TXB    CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 06, 4C, 42, 88, 10, FF, FF    RF_CLIF_CFG_BR_424_I_TXB    CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 03, 4C, 16, 00                RF_CLIF_CFG_BR_424_I_TXB    CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 4C, 15, 00                RF_CLIF_CFG_BR_424_I_TXB    CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 04, 52, 44, 26, 00            RF_CLIF_CFG_BR_848_I_RXB    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 52, 2D, 15, 25, 0D, 00    RF_CLIF_CFG_BR_848_I_RXB    CLIF_SIGPRO_RM_CONFIG1_REG
+#    A0, 0D, 06, 50, 42, 90, 10, FF, FF    RF_CLIF_CFG_BR_848_I_TXB    CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 06, 50, 4A, 21, 07, 00, 07    RF_CLIF_CFG_BR_848_I_TXB    CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 03, 50, 16, 00                RF_CLIF_CFG_BR_848_I_TXB    CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 50, 15, 00                RF_CLIF_CFG_BR_848_I_TXB    CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 06, 56, 2D, 05, 9E, 0C, 00    RF_CLIF_CFG_BR_212_I_RXF_P  CLIF_SIGPRO_RM_CONFIG1_REG
+#    A0, 0D, 04, 56, 44, 22, 00            RF_CLIF_CFG_BR_212_I_RXF_P  CLIF_ANA_RX_REG
+#    A0, 0D, 06, 5C, 2D, 05, 9E, 0C, 00    RF_CLIF_CFG_BR_424_I_RXF_P  CLIF_SIGPRO_RM_CONFIG1_REG
+#    A0, 0D, 04, 5C, 44, 26, 00            RF_CLIF_CFG_BR_424_I_RXF_P  CLIF_ANA_RX_REG
+#    A0, 0D, 06, 54, 42, 88, 10, FF, FF    RF_CLIF_CFG_BR_212_I_TXF    CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 06, 54, 4A, 33, 07, 01, 07    RF_CLIF_CFG_BR_212_I_TXF    CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 03, 54, 16, 00                RF_CLIF_CFG_BR_212_I_TXF    CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 54, 15, 00                RF_CLIF_CFG_BR_212_I_TXF    CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 06, 5A, 42, 90, 10, FF, FF    RF_CLIF_CFG_BR_424_I_TXF    CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 06, 5A, 4A, 31, 07, 01, 07    RF_CLIF_CFG_BR_424_I_TXF    CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 03, 5A, 16, 00                RF_CLIF_CFG_BR_424_I_TXF    CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 5A, 15, 00                RF_CLIF_CFG_BR_424_I_TXF    CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 06, 98, 2F, CF, 05, 80, 17    RF_CLIF_CFG_GTM_B           CLIF_SIGPRO_ADCBCM_CONFIG_REG
+#    A0, 0D, 06, 98, 42, 00, 02, FF, FF    RF_CLIF_CFG_GTM_B           CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 06, 9A, 42, 00, 02, FF, FF    RF_CLIF_CFG_GTM_FELICA      CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 06, 30, 44, 12, 90, 03, 00    RF_CLIF_CFG_TECHNO_T_RXF    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 6C, 44, A3, 90, 03, 00    RF_CLIF_CFG_BR_106_T_RXA    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 6C, 30, CF, 00, 08, 00    RF_CLIF_CFG_BR_106_T_RXA    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+#    A0, 0D, 06, 6C, 2F, 8F, 05, 80, 0C    RF_CLIF_CFG_BR_106_T_RXA    CLIF_SIGPRO_ADCBCM_CONFIG_REG
+#    A0, 0D, 06, 70, 2F, 8F, 05, 80, 12    RF_CLIF_CFG_BR_212_T_RXA    CLIF_SIGPRO_ADCBCM_CONFIG_REG
+#    A0, 0D, 06, 70, 30, CF, 00, 08, 00    RF_CLIF_CFG_BR_212_T_RXA    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+#    A0, 0D, 03, 70, 2E, 40                RF_CLIF_CFG_BR_212_T_RXA    CLIF_SIGPRO_CM_CONFIG_REG
+#    A0, 0D, 03, 70, 45, 30                RF_CLIF_CFG_BR_212_T_RXA    CLIF_ANA_CM_CONFIG_REG
+#    A0, 0D, 06, 70, 44, A3, 90, 03, 00    RF_CLIF_CFG_BR_212_T_RXA    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 74, 2F, 6F, 05, 80, 12    RF_CLIF_CFG_BR_424_T_RXA    CLIF_SIGPRO_ADCBCM_CONFIG_REG
+#    A0, 0D, 06, 74, 30, D5, 00, 40, 00    RF_CLIF_CFG_BR_424_T_RXA    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+#    A0, 0D, 06, 74, 44, A3, 90, 03, 00    RF_CLIF_CFG_BR_424_T_RXA    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 78, 2F, 3F, 07, 80, C1    RF_CLIF_CFG_BR_848_T_RXA    CLIF_SIGPRO_ADCBCM_CONFIG_REG
+#    A0, 0D, 06, 78, 30, 50, 00, 10, 00    RF_CLIF_CFG_BR_848_T_RXA    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+#    A0, 0D, 06, 78, 44, A3, 90, 03, 00    RF_CLIF_CFG_BR_848_T_RXA    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 7C, 2F, CF, 05, 80, 17    RF_CLIF_CFG_BR_106_T_RXB    CLIF_SIGPRO_ADCBCM_CONFIG_REG
+#    A0, 0D, 06, 7C, 30, C8, 00, 64, 00    RF_CLIF_CFG_BR_106_T_RXB    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+#    A0, 0D, 06, 7C, 44, A3, 90, 03, 00    RF_CLIF_CFG_BR_106_T_RXB    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 80, 2F, CF, 05, 80, 17    RF_CLIF_CFG_BR_212_T_RXB    CLIF_SIGPRO_ADCBCM_CONFIG_REG
+#    A0, 0D, 06, 80, 30, C8, 00, 64, 00    RF_CLIF_CFG_BR_212_T_RXB    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+#    A0, 0D, 06, 80, 44, A3, 90, 03, 00    RF_CLIF_CFG_BR_212_T_RXB    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 84, 2F, CF, 05, 80, 17    RF_CLIF_CFG_BR_424_T_RXB    CLIF_SIGPRO_ADCBCM_CONFIG_REG
+#    A0, 0D, 06, 84, 30, C8, 00, 64, 00    RF_CLIF_CFG_BR_424_T_RXB    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+#    A0, 0D, 06, 84, 44, A3, 90, 03, 00    RF_CLIF_CFG_BR_424_T_RXB    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 88, 2F, B1, 05, 80, 17    RF_CLIF_CFG_BR_848_T_RXB    CLIF_SIGPRO_ADCBCM_CONFIG_REG
+#    A0, 0D, 06, 88, 30, A8, 00, 64, 00    RF_CLIF_CFG_BR_848_T_RXB    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+#    A0, 0D, 06, 88, 44, A3, 90, 03, 00    RF_CLIF_CFG_BR_848_T_RXB    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 8E, 44, 12, 90, 03, 00    RF_CLIF_CFG_BR_212_T_RXF    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 94, 44, 12, 90, 03, 00    RF_CLIF_CFG_BR_424_T_RXF    CLIF_ANA_RX_REG
+#    A0, 0D, 03, 10, 43, 20                RF_CLIF_CFG_T_ACTIVE        CLIF_ANA_PBF_CONTROL_REG
+#    A0, 0D, 06, 10, 35, FF, 01, FF, 02    RF_CLIF_CFG_T_ACTIVE        CLIF_AGC_INPUT_REG
+#    A0, 0D, 06, 10, 34, F7, 7F, 00, 00    RF_CLIF_CFG_T_ACTIVE        CLIF_AGC_CONFIG1_REG
+#    A0, 0D, 06, 6A, 42, F8, 10, FF, FF    RF_CLIF_CFG_BR_106_T_TXA_A  CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 03, 6A, 16, 00                RF_CLIF_CFG_BR_106_T_TXA_A  CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 6A, 15, 01                RF_CLIF_CFG_BR_106_T_TXA_A  CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 06, 6A, 4A, 30, 0F, 01, 1F    RF_CLIF_CFG_BR_106_T_TXA_A  CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 06, 8C, 42, 88, 10, FF, FF    RF_CLIF_CFG_BR_212_T_TXF_A  CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 06, 8C, 4A, 33, 07, 01, 07    RF_CLIF_CFG_BR_212_T_TXF_A  CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 03, 8C, 16, 00                RF_CLIF_CFG_BR_212_T_TXF_A  CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 8C, 15, 00                RF_CLIF_CFG_BR_212_T_TXF_A  CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 06, 92, 42, 90, 10, FF, FF    RF_CLIF_CFG_BR_424_T_TXF_A  CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 06, 92, 4A, 31, 07, 01, 07    RF_CLIF_CFG_BR_424_T_TXF_A  CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 03, 92, 16, 00                RF_CLIF_CFG_BR_424_T_TXF_A  CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 92, 15, 00                RF_CLIF_CFG_BR_424_T_TXF_A  CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 24, 41, 40                RF_CLIF_CFG_TECHNO_T_TXA_P  CLIF_ANA_TX_CLK_CONTROL_REG
+#    A0, 0D, 06, 24, 42, 00, 02, FF, FF    RF_CLIF_CFG_TECHNO_T_TXA_P  CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 03, 28, 41, 40                RF_CLIF_CFG_TECHNO_T_TXB    CLIF_ANA_TX_CLK_CONTROL_REG
+#    A0, 0D, 03, 8A, 41, 40                RF_CLIF_CFG_BR_212_T_TXF_P  CLIF_ANA_TX_CLK_CONTROL_REG
+#    A0, 0D, 03, 90, 41, 40                RF_CLIF_CFG_BR_424_T_TXF_P  CLIF_ANA_TX_CLK_CONTROL_REG
+#    A0, 0D, 03, 08, 40, 10                RF_CLIF_CFG_I_PASSIVE       CLIF_ANA_NFCLD_REG
+#    A0, 0D, 06, 08, 45, C0, 82, 00, 00    RF_CLIF_CFG_I_PASSIVE       CLIF_ANA_CM_CONFIG_REG
+#    A0, 0D, 06, 0A, 44, A3, 90, 03, 00    RF_CLIF_CFG_I_ACTIVE        CLIF_ANA_RX_REG
+#    A0, 0D, 06, 0A, 45, 80, 40, 00, 00    RF_CLIF_CFG_I_ACTIVE        CLIF_ANA_CM_CONFIG_REG
+#    A0, 0D, 06, 0A, 30, C8, 00, 64, 00    RF_CLIF_CFG_I_ACTIVE        CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+#    A0, 0D, 06, 0A, 2F, AF, 05, 80, 17    RF_CLIF_CFG_I_ACTIVE        CLIF_SIGPRO_ADCBCM_CONFIG_REG
+#    A0, 0D, 03, 0A, 48, 10                RF_CLIF_CFG_I_ACTIVE        CLIF_ANA_CLK_MAN_REG
+#    A0, 0D, 06, 0A, 34, 26, 65, E5, 03    RF_CLIF_CFG_I_ACTIVE        CLIF_AGC_CONFIG1_REG
+#    A0, 0D, 06, 0A, 33, 0F, 01, 00, 70    RF_CLIF_CFG_I_ACTIVE        CLIF_AGC_CONFIG0_REG
+#    A0, 0D, 03, 0A, 40, 00                RF_CLIF_CFG_I_ACTIVE        CLIF_ANA_NFCLD_REG
+#
+# *** ALMSL FW VERSION = 10.05.03 ***
+NXP_RF_CONF_BLK_1={
+    20, 02, FA, 20,
+    A0, 0D, 03, 00, 40, 03,
+    A0, 0D, 06, 00, FF, 05, 04, 06, 00,
+    A0, 0D, 06, 00, 35, FF, 01, FF, 02,
+    A0, 0D, 06, 00, 33, 07, 40, 00, 00,
+    A0, 0D, 03, 02, 40, 00,
+    A0, 0D, 03, 04, 43, 20,
+    A0, 0D, 03, 04, 47, 02,
+    A0, 0D, 06, 04, 35, F4, 01, F4, 01,
+    A0, 0D, 06, 04, FF, 05, 00, 00, 00,
+    A0, 0D, 06, 05, 45, 80, 40, 00, 00,
+    A0, 0D, 06, 05, 35, FF, 01, FF, 02,
+    A0, 0D, 06, 05, 33, 07, 40, 00, 00,
+    A0, 0D, 06, 06, 44, A3, 90, 03, 00,
+    A0, 0D, 03, 06, 47, 02,
+    A0, 0D, 06, 06, 35, C0, 03, C0, 02,
+    A0, 0D, 06, 06, 34, F7, 7F, 00, 10,
+    A0, 0D, 06, 06, 33, 03, 40, 00, 00,
+    A0, 0D, 06, 06, 30, B0, 00, 10, 00,
+    A0, 0D, 06, 06, 2F, AF, 05, 80, 17,
+    A0, 0D, 06, 06, 03, 00, 71, 00, 20,
+    A0, 0D, 03, 06, 43, 20,
+    A0, 0D, 06, 06, 42, 00, 03, F2, F2,
+    A0, 0D, 03, 06, 41, 40,
+    A0, 0D, 03, 06, 37, 08,
+    A0, 0D, 03, 06, 16, 00,
+    A0, 0D, 03, 06, 15, 00,
+    A0, 0D, 03, 06, 3F, 04,
+    A0, 0D, 03, 06, 80, 03,
+    A0, 0D, 06, 06, FF, 05, 00, 00, 00,
+    A0, 0D, 03, 07, 3F, 00,
+    A0, 0D, 06, 07, 35, FF, 01, FF, 02,
+    A0, 0D, 06, 07, 33, 07, 40, 00, 00
+}
+
+NXP_RF_CONF_BLK_2={
+    20, 02, F8, 1F,
+    A0, 0D, 06, 18, 34, 00, 00, E1, 03,
+    A0, 0D, 06, 18, 33, 0F, 83, 00, 00,
+    A0, 0D, 06, 1C, 34, 00, 00, E1, 03,
+    A0, 0D, 06, 1C, 33, 0F, 83, 00, 00,
+    A0, 0D, 06, 20, 4A, 00, 00, 00, 00,
+    A0, 0D, 06, 20, 42, 88, 10, FF, FF,
+    A0, 0D, 03, 20, 16, 00,
+    A0, 0D, 03, 20, 15, 00,
+    A0, 0D, 04, 22, 44, 22, 00,
+    A0, 0D, 06, 22, 2D, 50, 44, 0C, 00,
+    A0, 0D, 04, 32, 03, 40, 3D,
+    A0, 0D, 06, 32, 42, F8, 10, FF, FF,
+    A0, 0D, 03, 32, 16, 00,
+    A0, 0D, 03, 32, 15, 01,
+    A0, 0D, 03, 32, 0D, 22,
+    A0, 0D, 03, 32, 14, 22,
+    A0, 0D, 06, 32, 4A, 33, 07, 00, 08,
+    A0, 0D, 06, 34, 2D, 24, 47, 0C, 00,
+    A0, 0D, 06, 34, 34, 00, 00, EC, 03,
+    A0, 0D, 06, 34, 33, 0F, 01, 01, 70,
+    A0, 0D, 04, 34, 44, 21, 00,
+    A0, 0D, 06, 38, 4A, 33, 07, 00, 08,
+    A0, 0D, 06, 38, 42, 68, 10, FF, FF,
+    A0, 0D, 03, 38, 16, 00,
+    A0, 0D, 03, 38, 15, 00,
+    A0, 0D, 04, 3A, 44, 26, 00,
+    A0, 0D, 06, 3A, 2D, 15, 47, 0D, 00,
+    A0, 0D, 06, 3A, 34, 00, 00, E1, 03,
+    A0, 0D, 06, 3A, 33, 0B, 83, 00, 00,
+    A0, 0D, 06, 3C, 4A, 52, 07, 00, 1B,
+    A0, 0D, 06, 3C, 42, 68, 10, FF, FF
+}
+
+NXP_RF_CONF_BLK_3={
+    20, 02, F9, 20,
+    A0, 0D, 03, 3C, 16, 00,
+    A0, 0D, 03, 3C, 15, 00,
+    A0, 0D, 04, 3E, 44, 26, 00,
+    A0, 0D, 06, 3E, 2D, 15, 47, 0D, 00,
+    A0, 0D, 06, 3E, 34, 00, 00, E1, 03,
+    A0, 0D, 06, 3E, 33, 0B, 83, 00, 00,
+    A0, 0D, 06, 40, 42, F0, 10, FF, FF,
+    A0, 0D, 03, 40, 0D, 02,
+    A0, 0D, 03, 40, 14, 02,
+    A0, 0D, 06, 40, 4A, 12, 07, 00, 00,
+    A0, 0D, 03, 40, 16, 00,
+    A0, 0D, 03, 40, 15, 00,
+    A0, 0D, 04, 42, 44, 26, 00,
+    A0, 0D, 06, 42, 2D, 15, 47, 0D, 00,
+    A0, 0D, 06, 42, 34, 00, 00, E1, 03,
+    A0, 0D, 06, 42, 33, 0B, 83, 00, 00,
+    A0, 0D, 04, 46, 44, 26, 00,
+    A0, 0D, 06, 46, 2D, 15, 25, 0D, 00,
+    A0, 0D, 06, 44, 4A, 21, 07, 00, 07,
+    A0, 0D, 06, 44, 42, 88, 10, FF, FF,
+    A0, 0D, 03, 44, 16, 00,
+    A0, 0D, 03, 44, 15, 00,
+    A0, 0D, 04, 4A, 44, 21, 00,
+    A0, 0D, 06, 4A, 2D, 15, 9D, 0D, 00,
+    A0, 0D, 06, 48, 4A, 21, 07, 00, 07,
+    A0, 0D, 06, 48, 42, 88, 10, FF, FF,
+    A0, 0D, 03, 48, 16, 00,
+    A0, 0D, 03, 48, 15, 00,
+    A0, 0D, 04, 4E, 44, 26, 00,
+    A0, 0D, 06, 4E, 2D, 15, 25, 0D, 00,
+    A0, 0D, 06, 4C, 4A, 21, 07, 00, 07,
+    A0, 0D, 06, 4C, 42, 88, 10, FF, FF
+}
+
+NXP_RF_CONF_BLK_4={
+    20, 02, F4, 1F,
+    A0, 0D, 03, 4C, 16, 00,
+    A0, 0D, 03, 4C, 15, 00,
+    A0, 0D, 04, 52, 44, 26, 00,
+    A0, 0D, 06, 52, 2D, 15, 25, 0D, 00,
+    A0, 0D, 06, 50, 42, 90, 10, FF, FF,
+    A0, 0D, 06, 50, 4A, 21, 07, 00, 07,
+    A0, 0D, 03, 50, 16, 00,
+    A0, 0D, 03, 50, 15, 00,
+    A0, 0D, 06, 56, 2D, 05, 9E, 0C, 00,
+    A0, 0D, 04, 56, 44, 22, 00,
+    A0, 0D, 06, 5C, 2D, 05, 9E, 0C, 00,
+    A0, 0D, 04, 5C, 44, 26, 00,
+    A0, 0D, 06, 54, 42, 88, 10, FF, FF,
+    A0, 0D, 06, 54, 4A, 33, 07, 01, 07,
+    A0, 0D, 03, 54, 16, 00,
+    A0, 0D, 03, 54, 15, 00,
+    A0, 0D, 06, 5A, 42, 90, 10, FF, FF,
+    A0, 0D, 06, 5A, 4A, 31, 07, 01, 07,
+    A0, 0D, 03, 5A, 16, 00,
+    A0, 0D, 03, 5A, 15, 00,
+    A0, 0D, 06, 98, 2F, CF, 05, 80, 17,
+    A0, 0D, 06, 98, 42, 00, 03, F2, F2,
+    A0, 0D, 06, 9A, 42, 00, 03, F2, F2,
+    A0, 0D, 06, 30, 44, 12, 90, 03, 00,
+    A0, 0D, 06, 6C, 44, A3, 90, 03, 00,
+    A0, 0D, 06, 6C, 30, CF, 00, 08, 00,
+    A0, 0D, 06, 6C, 2F, 8F, 05, 80, 0C,
+    A0, 0D, 06, 70, 2F, 8F, 05, 80, 12,
+    A0, 0D, 06, 70, 30, CF, 00, 08, 00,
+    A0, 0D, 03, 70, 2E, 40,
+    A0, 0D, 03, 70, 45, 30
+}
+
+NXP_RF_CONF_BLK_5={
+    20, 02, F4, 1C,
+    A0, 0D, 06, 70, 44, A3, 90, 03, 00,
+    A0, 0D, 06, 74, 2F, 6F, 05, 80, 12,
+    A0, 0D, 06, 74, 30, D5, 00, 40, 00,
+    A0, 0D, 06, 74, 44, A3, 90, 03, 00,
+    A0, 0D, 06, 78, 2F, 3F, 07, 80, C1,
+    A0, 0D, 06, 78, 30, 50, 00, 10, 00,
+    A0, 0D, 06, 78, 44, A3, 90, 03, 00,
+    A0, 0D, 06, 7C, 2F, CF, 05, 80, 17,
+    A0, 0D, 06, 7C, 30, B0, 00, 10, 00,
+    A0, 0D, 06, 7C, 44, A3, 90, 03, 00,
+    A0, 0D, 06, 80, 2F, CF, 05, 80, 17,
+    A0, 0D, 06, 80, 30, C8, 00, 64, 00,
+    A0, 0D, 06, 80, 44, A3, 90, 03, 00,
+    A0, 0D, 06, 84, 2F, CF, 05, 80, 17,
+    A0, 0D, 06, 84, 30, C8, 00, 64, 00,
+    A0, 0D, 06, 84, 44, A3, 90, 03, 00,
+    A0, 0D, 06, 88, 2F, B1, 05, 80, 17,
+    A0, 0D, 06, 88, 30, A8, 00, 64, 00,
+    A0, 0D, 06, 88, 44, A3, 90, 03, 00,
+    A0, 0D, 06, 8E, 44, 12, 90, 03, 00,
+    A0, 0D, 06, 94, 44, 12, 90, 03, 00,
+    A0, 0D, 03, 10, 43, 20,
+    A0, 0D, 06, 10, 35, FF, 01, FF, 02,
+    A0, 0D, 06, 10, 34, F7, 7F, 00, 00,
+    A0, 0D, 06, 6A, 42, F8, 10, FF, FF,
+    A0, 0D, 03, 6A, 16, 00,
+    A0, 0D, 03, 6A, 15, 01,
+    A0, 0D, 06, 6A, 4A, 30, 0F, 01, 1F
+}
+
+NXP_RF_CONF_BLK_6={
+    20, 02, AF, 17,
+    A0, 0D, 06, 8C, 42, 88, 10, FF, FF,
+    A0, 0D, 06, 8C, 4A, 33, 07, 01, 07,
+    A0, 0D, 03, 8C, 16, 00,
+    A0, 0D, 03, 8C, 15, 00,
+    A0, 0D, 06, 92, 42, 90, 10, FF, FF,
+    A0, 0D, 06, 92, 4A, 31, 07, 01, 07,
+    A0, 0D, 03, 92, 16, 00,
+    A0, 0D, 03, 92, 15, 00,
+    A0, 0D, 03, 24, 41, 40,
+    A0, 0D, 06, 24, 42, 00, 03, F2, F2,
+    A0, 0D, 03, 28, 41, 40,
+    A0, 0D, 03, 8A, 41, 40,
+    A0, 0D, 03, 90, 41, 40,
+    A0, 0D, 03, 08, 40, 10,
+    A0, 0D, 06, 08, 45, C0, 82, 00, 00,
+    A0, 0D, 06, 0A, 44, A3, 90, 03, 00,
+    A0, 0D, 06, 0A, 45, 80, 40, 00, 00,
+    A0, 0D, 06, 0A, 30, C8, 00, 64, 00,
+    A0, 0D, 06, 0A, 2F, AF, 05, 80, 17,
+    A0, 0D, 03, 0A, 48, 10,
+    A0, 0D, 06, 0A, 34, 26, 65, E5, 03,
+    A0, 0D, 06, 0A, 33, 0F, 01, 00, 70,
+    A0, 0D, 03, 0A, 40, 00
+}
+
+
+###############################################################################
+## Set configuration optimization decision setting
+## Enable    = 0x01
+## Disable   = 0x00
+NXP_SET_CONFIG_ALWAYS=0x00
+
+###############################################################################
+# Core configuration extensions
+# It includes
+# A002      - Disable/Enable Clock Request
+# A009      - Time-out before standby
+# A012      - NFCEE interface 2 configuration
+# A040      - Low Power Card Detector Enable
+# A041      - Low Power Card Detector Threshold
+# A042      - Low Power Card Detector Sampling
+# A043      - Low Power Card Detector Hybrid
+# A05E      - Send RID automatically in Jewel Reader mode
+# A061      - Retry after LPCD
+# A096      - Notify all AIDs
+# A0DD      - Retry on SWP2 interface
+# A0EC      - Disable/Enable SWP1 interface
+# A0ED      - Disable/Enable SWP2 interface
+# A0F2      - SVDD_PWR_REQ enable
+NXP_CORE_CONF_EXTN={20, 02, B7, 14,
+        A0, 02, 01, 01,
+        A0, 09, 02, E8, 03,
+        A0, 12, 01, 00,
+        A0, 40, 01, 01,
+        A0, 41, 01, 05,
+        A0, 42, 01, 0F,
+        A0, 43, 01, 03,
+        A0, 5E, 01, 01,
+        A0, 61, 01, 53,
+        A0, 96, 01, 01,
+        A0, DD, 01, 2D,
+        A0, EC, 01, 01,
+        A0, ED, 01, 00,
+        A0, F2, 01, 00,
+        A0, 47, 02, 00, 27,
+        A0, CD, 01, 1F,
+        A0, CB, 01, 10,
+        A0, 1D, 11, 52, 33, 14, 17, 00, AA, 85, 00, 80, 55, 2A, 04, 00, 63, 00, 00, 00,
+        A0, 1E, 11, 1B, 13, 14, 14, 00, 6F, 97, 00, 00, 00, 10, 04, 00, 63, 02, 00, 00,
+        A0, 92, 45, 23, 04, 50, 10, 00, 00, 00, 14, 00, 20, 00, 14, 00, B3, 00, 06, 00, 20, 01, 06, 00, FF, 03, 06, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00
+        }
+
+###############################################################################
+# Core configuration rf field filter settings to enable set to 01 to disable set to 00 last bit
+NXP_CORE_RF_FIELD={ 20, 02, 05, 01, A0, 62, 01, 00}
+###############################################################################
+# To enable i2c fragmentation set i2c fragmentation enable 0x01 to disable set to 0x00
+NXP_I2C_FRAGMENTATION_ENABLED=0x00
+
+###############################################################################
+# Core configuration settings
+# It includes
+# 18        - Poll Mode NFC-F:   PF_BIT_RATE
+# 21        - Poll Mode ISO-DEP: PI_BIT_RATE
+# 28        - Poll Mode NFC-DEP: PN_NFC_DEP_SPEED
+# 30        - Lis. Mode NFC-A:   LA_BIT_FRAME_SDD
+# 31        - Lis. Mode NFC-A:   LA_PLATFORM_CONFIG
+# 33        - Lis. Mode NFC-A:   LA_NFCID1
+# 50        - Lis. Mode NFC-F:   LF_PROTOCOL_TYPE
+# 54        - Lis. Mode NFC-F:   LF_CON_BITR_F
+# 5B        - Lis. Mode ISO-DEP: LI_BIT_RATE
+# 60        - Lis. Mode NFC-DEP: LN_WT
+# 80        - Other Param.:      RF_FIELD_INFO
+# 81        - Other Param.:      RF_NFCEE_ACTION
+# 82        - Other Param.:      NFCDEP_OP
+NXP_CORE_CONF={20, 02, 2A, 0E,
+        18, 01, 01,
+        21, 01, 00,
+        28, 01, 00,
+        30, 01, 04,
+        31, 01, 00,
+        33, 00,
+        50, 01, 02,
+        54, 01, 06,
+        5B, 01, 00,
+        60, 01, 0E,
+        80, 01, 01,
+        81, 01, 01,
+        82, 01, 0E,
+        32, 01, 60
+        }
+
+###############################################################################
+# Mifare Classic Key settings
+#NXP_CORE_MFCKEY_SETTING={20, 02, 25,04, A0, 51, 06, A0, A1, A2, A3, A4, A5,
+#                                     A0, 52, 06, D3, F7, D3, F7, D3, F7,
+#                                     A0, 53, 06, FF, FF, FF, FF, FF, FF,
+#                                     A0, 54, 06, 00, 00, 00, 00, 00, 00}
+
+###############################################################################
+# Default SE Options
+# No secure element 0x00
+# eSE               0x01
+# UICC              0x02
+
+NXP_DEFAULT_SE=0x02
+
+###############################################################################
+#Enable SWP full power mode when phone is power off
+NXP_SWP_FULL_PWR_ON=0x00
+
+###############################################################################
+#### Select the CHIP ####
+#PN547C2            0x01
+#PN65T              0x02
+#PN548AD            0x03
+#PN66T              0x04
+#PN551              0x05
+#PN67T              0x06
+
+NXP_NFC_CHIP=0x05
+###############################################################################
+# CE when Screen state is locked
+# Disable           0x00
+# Enable            0x01
+NXP_CE_ROUTE_STRICT_DISABLE=0x01
+
+#Timeout in secs to get NFCEE Discover notification
+NXP_DEFAULT_NFCEE_DISC_TIMEOUT=20
+
+NXP_DEFAULT_NFCEE_TIMEOUT=0x06
+
+#Timeout in secs
+NXP_SWP_RD_START_TIMEOUT=0x0A
+
+#Timeout in secs
+NXP_SWP_RD_TAG_OP_TIMEOUT=0x01
+
+###############################################################################
+#Set the default AID route Location :
+#This settings will be used when application does not set this parameter
+# host 0x00
+# eSE  0x01
+# UICC 0x02
+DEFAULT_AID_ROUTE=0x00
+
+###############################################################################
+#Set the Mifare Desfire route Location :
+#This settings will be used when application does not set this parameter
+# host 0x00
+# eSE  0x01
+# UICC 0x02
+DEFAULT_DESFIRE_ROUTE=0x02
+
+###############################################################################
+#Set the Mifare CLT route Location :
+#This settings will be used when application does not set this parameter
+# host 0x00
+# eSE  0x01
+# UICC 0x02
+DEFAULT_MIFARE_CLT_ROUTE=0x02
+
+###############################################################################
+#Set the default AID Power state :
+#This settings will be used when application does not set this parameter
+# bit pos 0 = Switch On
+# bit pos 1 = Switch Off
+# bit pos 2 = Battery Off
+# bit pos 3 = Screen Lock
+# bit pos 4 = Screen Off
+DEFAULT_AID_PWR_STATE=0x19
+
+###############################################################################
+#Set the Mifare Desfire Power state :
+#This settings will be used when application does not set this parameter
+# bit pos 0 = Switch On
+# bit pos 1 = Switch Off
+# bit pos 2 = Battery Off
+# bit pos 3 = Screen Lock
+# bit pos 4 = Screen Off
+DEFAULT_DESFIRE_PWR_STATE=0x1B
+
+###############################################################################
+#Set the Mifare CLT Power state :
+#This settings will be used when application does not set this parameter
+# bit pos 0 = Switch On
+# bit pos 1 = Switch Off
+# bit pos 2 = Battery Off
+# bit pos 3 = Screen Lock
+# bit pos 4 = Screen Off
+DEFAULT_MIFARE_CLT_PWR_STATE=0x1B
+
+###############################################################################
+# AID Matching platform options
+# AID_MATCHING_L 0x01
+# AID_MATCHING_K 0x02
+AID_MATCHING_PLATFORM=0x01
+###############################################################################
+#CHINA_TIANJIN_RF_SETTING
+#Enable  0x01
+#Disable 0x00
+NXP_CHINA_TIANJIN_RF_ENABLED=0x01
+###############################################################################
+#SWP_SWITCH_TIMEOUT_SETTING
+# Allowed range of swp timeout setting is 0x00 to 0x3C [0 - 60].
+# Timeout in milliseconds, for example
+# No Timeout  0x00
+# 10 millisecond timeout 0x0A
+NXP_SWP_SWITCH_TIMEOUT=0x0A
+###############################################################################
+#Dynamic RSSI feature enable
+# Disable           0x00
+# Enable            0x01
+NXP_AGC_DEBUG_ENABLE=0x00
+###############################################################################
+# UICC mode supported
+# Disable           0x00
+# Enable            0x01
+NXP_DUAL_UICC_ENABLE=0x00
+###############################################################################
+#Config to allow adding aids
+#NFC on/off is required after this config
+#1 = enabling adding aid  to NFCC routing table.
+#0 = disabling adding aid to NFCC routing table.
+NXP_ENABLE_ADD_AID=0x01
+###############################################################################
+# Enable/Disable checking default proto SE Id
+# Disable           0x00
+# Enable            0x01
+NXP_CHECK_DEFAULT_PROTO_SE_ID=0x01
--- a/nfc/libnfc-nxp_RF-hi6250-pra.conf
+++ b/nfc/libnfc-nxp_RF-hi6250-pra.conf
@ -0,0 +1,502 @@
+###############################################################################
+# NXP RF ALMSL configuration settings for FW VERSION = 10.05.03
+#
+#    A0, 0D, 03, 00, 40, 01                RF_CLIF_CFG_BOOT            CLIF_ANA_NFCLD_REG
+#    A0, 0D, 06, 00, FF, 05, 04, 06, 00    RF_CLIF_CFG_BOOT            SMU_PMU_REG (0x40024010)
+#    A0, 0D, 06, 00, 35, FF, 01, FF, 02    RF_CLIF_CFG_BOOT            CLIF_AGC_INPUT_REG
+#    A0, 0D, 06, 00, 33, 07, 40, 00, 00    RF_CLIF_CFG_BOOT            CLIF_AGC_CONFIG0_REG
+#    A0, 0D, 03, 02, 40, 00                RF_CLIF_CFG_IDLE            CLIF_ANA_NFCLD_REG
+#    A0, 0D, 03, 04, 43, 20                RF_CLIF_CFG_INITIATOR       CLIF_ANA_PBF_CONTROL_REG
+#    A0, 0D, 03, 04, 47, 02                RF_CLIF_CFG_INITIATOR       CLIF_ANA_AGC_REG
+#    A0, 0D, 06, 04, 35, F4, 01, F4, 01    RF_CLIF_CFG_INITIATOR       CLIF_AGC_INPUT_REG
+#    A0, 0D, 06, 04, FF, 05, 00, 00, 00    RF_CLIF_CFG_INITIATOR       SMU_PMU_REG (0x40024010)
+#    A0, 0D, 06, 05, 45, 80, 40, 00, 00    RF_CLIF_CFG_INITIATOR       CLIF_ANA_CM_CONFIG_REG
+#    A0, 0D, 06, 05, 35, FF, 01, FF, 02    RF_CLIF_CFG_INITIATOR       CLIF_AGC_INPUT_REG
+#    A0, 0D, 06, 05, 33, 07, 40, 00, 00    RF_CLIF_CFG_INITIATOR       CLIF_AGC_CONFIG0_REG
+#    A0, 0D, 06, 06, 44, A3, 90, 03, 00    RF_CLIF_CFG_TARGET          CLIF_ANA_RX_REG
+#    A0, 0D, 03, 06, 47, 02                RF_CLIF_CFG_TARGET          CLIF_ANA_AGC_REG
+#    A0, 0D, 06, 06, 35, FF, 03, FF, 03    RF_CLIF_CFG_TARGET          CLIF_AGC_INPUT_REG
+#    A0, 0D, 06, 06, 34, F7, 7F, 00, 10    RF_CLIF_CFG_TARGET          CLIF_AGC_CONFIG1_REG
+#    A0, 0D, 06, 06, 33, 03, 40, 00, 00    RF_CLIF_CFG_TARGET          CLIF_AGC_CONFIG0_REG
+#    A0, 0D, 06, 06, 30, C8, 00, 64, 00    RF_CLIF_CFG_TARGET          CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+#    A0, 0D, 06, 06, 2F, AF, 05, 80, 17    RF_CLIF_CFG_TARGET          CLIF_SIGPRO_ADCBCM_CONFIG_REG
+#    A0, 0D, 06, 06, 03, 00, 6D, 00, 20    RF_CLIF_CFG_TARGET          CLIF_TRANSCEIVE_CONTROL_REG
+#    A0, 0D, 03, 06, 43, 20                RF_CLIF_CFG_TARGET          CLIF_ANA_PBF_CONTROL_REG
+#    A0, 0D, 06, 06, 42, 00, 02, FF, FF    RF_CLIF_CFG_TARGET          CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 03, 06, 41, 40                RF_CLIF_CFG_TARGET          CLIF_ANA_TX_CLK_CONTROL_REG
+#    A0, 0D, 03, 06, 37, 08                RF_CLIF_CFG_TARGET          CLIF_TX_CONTROL_REG
+#    A0, 0D, 03, 06, 16, 00                RF_CLIF_CFG_TARGET          CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 06, 15, 00                RF_CLIF_CFG_TARGET          CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 06, 3F, 04                RF_CLIF_CFG_TARGET          CLIF_TEST_CONTROL_REG
+#    A0, 0D, 03, 06, 80, 03                RF_CLIF_CFG_TARGET          CLIF_SPARE_REG
+#    A0, 0D, 06, 06, FF, 05, 00, 00, 00    RF_CLIF_CFG_TARGET          SMU_PMU_REG (0x40024010)
+#    A0, 0D, 03, 07, 3F, 00                RF_CLIF_CFG_TARGET          CLIF_TEST_CONTROL_REG
+#    A0, 0D, 06, 07, 35, FF, 01, FF, 02    RF_CLIF_CFG_TARGET          CLIF_AGC_INPUT_REG
+#    A0, 0D, 06, 07, 33, 07, 40, 00, 00    RF_CLIF_CFG_TARGET          CLIF_AGC_CONFIG0_REG
+#    A0, 0D, 06, 18, 34, 00, 00, E1, 03    RF_CLIF_CFG_TECHNO_I_RXB    CLIF_AGC_CONFIG1_REG
+#    A0, 0D, 06, 18, 33, 0F, 83, 00, 00    RF_CLIF_CFG_TECHNO_I_RXB    CLIF_AGC_CONFIG0_REG
+#    A0, 0D, 06, 1C, 34, 00, 00, E1, 03    RF_CLIF_CFG_TECHNO_I_RXF_P  CLIF_AGC_CONFIG1_REG
+#    A0, 0D, 06, 1C, 33, 0F, 83, 00, 00    RF_CLIF_CFG_TECHNO_I_RXF_P  CLIF_AGC_CONFIG0_REG
+#    A0, 0D, 06, 20, 4A, 00, 00, 00, 00    RF_CLIF_CFG_TECHNO_I_TX15693CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 06, 20, 42, 88, 10, FF, FF    RF_CLIF_CFG_TECHNO_I_TX15693CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 03, 20, 16, 00                RF_CLIF_CFG_TECHNO_I_TX15693CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 20, 15, 00                RF_CLIF_CFG_TECHNO_I_TX15693CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 04, 22, 44, 22, 00            RF_CLIF_CFG_TECHNO_I_RX15693CLIF_ANA_RX_REG
+#    A0, 0D, 06, 22, 2D, 50, 44, 0C, 00    RF_CLIF_CFG_TECHNO_I_RX15693CLIF_SIGPRO_RM_CONFIG1_REG
+#    A0, 0D, 04, 32, 03, 40, 3D            RF_CLIF_CFG_BR_106_I_TXA    CLIF_TRANSCEIVE_CONTROL_REG
+#    A0, 0D, 06, 32, 42, F8, 10, FF, FF    RF_CLIF_CFG_BR_106_I_TXA    CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 03, 32, 16, 00                RF_CLIF_CFG_BR_106_I_TXA    CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 32, 15, 01                RF_CLIF_CFG_BR_106_I_TXA    CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 32, 0D, 22                RF_CLIF_CFG_BR_106_I_TXA    CLIF_TX_DATA_MOD_REG
+#    A0, 0D, 03, 32, 14, 22                RF_CLIF_CFG_BR_106_I_TXA    CLIF_TX_SYMBOL23_MOD_REG
+#    A0, 0D, 06, 32, 4A, 33, 07, 00, 08    RF_CLIF_CFG_BR_106_I_TXA    CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 06, 34, 2D, 24, 47, 0C, 00    RF_CLIF_CFG_BR_106_I_RXA_P  CLIF_SIGPRO_RM_CONFIG1_REG
+#    A0, 0D, 06, 34, 34, 00, 00, EC, 03    RF_CLIF_CFG_BR_106_I_RXA_P  CLIF_AGC_CONFIG1_REG
+#    A0, 0D, 06, 34, 33, 0F, 01, 01, 70    RF_CLIF_CFG_BR_106_I_RXA_P  CLIF_AGC_CONFIG0_REG
+#    A0, 0D, 04, 34, 44, 21, 00            RF_CLIF_CFG_BR_106_I_RXA_P  CLIF_ANA_RX_REG
+#    A0, 0D, 06, 38, 4A, 33, 07, 00, 08    RF_CLIF_CFG_BR_212_I_TXA    CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 06, 38, 42, 68, 10, FF, FF    RF_CLIF_CFG_BR_212_I_TXA    CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 03, 38, 16, 00                RF_CLIF_CFG_BR_212_I_TXA    CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 38, 15, 00                RF_CLIF_CFG_BR_212_I_TXA    CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 04, 3A, 44, 26, 00            RF_CLIF_CFG_BR_212_I_RXA    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 3A, 2D, 15, 47, 0D, 00    RF_CLIF_CFG_BR_212_I_RXA    CLIF_SIGPRO_RM_CONFIG1_REG
+#    A0, 0D, 06, 3A, 34, 00, 00, E1, 03    RF_CLIF_CFG_BR_212_I_RXA    CLIF_AGC_CONFIG1_REG
+#    A0, 0D, 06, 3A, 33, 0B, 83, 00, 00    RF_CLIF_CFG_BR_212_I_RXA    CLIF_AGC_CONFIG0_REG
+#    A0, 0D, 06, 3C, 4A, 52, 07, 00, 1B    RF_CLIF_CFG_BR_424_I_TXA    CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 06, 3C, 42, 68, 10, FF, FF    RF_CLIF_CFG_BR_424_I_TXA    CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 03, 3C, 16, 00                RF_CLIF_CFG_BR_424_I_TXA    CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 3C, 15, 00                RF_CLIF_CFG_BR_424_I_TXA    CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 04, 3E, 44, 26, 00            RF_CLIF_CFG_BR_424_I_RXA    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 3E, 2D, 15, 47, 0D, 00    RF_CLIF_CFG_BR_424_I_RXA    CLIF_SIGPRO_RM_CONFIG1_REG
+#    A0, 0D, 06, 3E, 34, 00, 00, E1, 03    RF_CLIF_CFG_BR_424_I_RXA    CLIF_AGC_CONFIG1_REG
+#    A0, 0D, 06, 3E, 33, 0B, 83, 00, 00    RF_CLIF_CFG_BR_424_I_RXA    CLIF_AGC_CONFIG0_REG
+#    A0, 0D, 06, 40, 42, F0, 10, FF, FF    RF_CLIF_CFG_BR_848_I_TXA    CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 03, 40, 0D, 02                RF_CLIF_CFG_BR_848_I_TXA    CLIF_TX_DATA_MOD_REG
+#    A0, 0D, 03, 40, 14, 02                RF_CLIF_CFG_BR_848_I_TXA    CLIF_TX_SYMBOL23_MOD_REG
+#    A0, 0D, 06, 40, 4A, 12, 07, 00, 00    RF_CLIF_CFG_BR_848_I_TXA    CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 03, 40, 16, 00                RF_CLIF_CFG_BR_848_I_TXA    CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 40, 15, 00                RF_CLIF_CFG_BR_848_I_TXA    CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 04, 42, 44, 26, 00            RF_CLIF_CFG_BR_848_I_RXA    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 42, 2D, 15, 47, 0D, 00    RF_CLIF_CFG_BR_848_I_RXA    CLIF_SIGPRO_RM_CONFIG1_REG
+#    A0, 0D, 06, 42, 34, 00, 00, E1, 03    RF_CLIF_CFG_BR_848_I_RXA    CLIF_AGC_CONFIG1_REG
+#    A0, 0D, 06, 42, 33, 0B, 83, 00, 00    RF_CLIF_CFG_BR_848_I_RXA    CLIF_AGC_CONFIG0_REG
+#    A0, 0D, 04, 46, 44, 26, 00            RF_CLIF_CFG_BR_106_I_RXB    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 46, 2D, 15, 25, 0D, 00    RF_CLIF_CFG_BR_106_I_RXB    CLIF_SIGPRO_RM_CONFIG1_REG
+#    A0, 0D, 06, 44, 4A, 21, 07, 00, 07    RF_CLIF_CFG_BR_106_I_TXB    CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 06, 44, 42, 88, 10, FF, FF    RF_CLIF_CFG_BR_106_I_TXB    CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 03, 44, 16, 00                RF_CLIF_CFG_BR_106_I_TXB    CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 44, 15, 00                RF_CLIF_CFG_BR_106_I_TXB    CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 04, 4A, 44, 21, 00            RF_CLIF_CFG_BR_212_I_RXB    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 4A, 2D, 15, 9D, 0D, 00    RF_CLIF_CFG_BR_212_I_RXB    CLIF_SIGPRO_RM_CONFIG1_REG
+#    A0, 0D, 06, 48, 4A, 21, 07, 00, 07    RF_CLIF_CFG_BR_212_I_TXB    CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 06, 48, 42, 88, 10, FF, FF    RF_CLIF_CFG_BR_212_I_TXB    CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 03, 48, 16, 00                RF_CLIF_CFG_BR_212_I_TXB    CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 48, 15, 00                RF_CLIF_CFG_BR_212_I_TXB    CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 04, 4E, 44, 26, 00            RF_CLIF_CFG_BR_424_I_RXB    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 4E, 2D, 15, 25, 0D, 00    RF_CLIF_CFG_BR_424_I_RXB    CLIF_SIGPRO_RM_CONFIG1_REG
+#    A0, 0D, 06, 4C, 4A, 21, 07, 00, 07    RF_CLIF_CFG_BR_424_I_TXB    CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 06, 4C, 42, 88, 10, FF, FF    RF_CLIF_CFG_BR_424_I_TXB    CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 03, 4C, 16, 00                RF_CLIF_CFG_BR_424_I_TXB    CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 4C, 15, 00                RF_CLIF_CFG_BR_424_I_TXB    CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 04, 52, 44, 26, 00            RF_CLIF_CFG_BR_848_I_RXB    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 52, 2D, 15, 25, 0D, 00    RF_CLIF_CFG_BR_848_I_RXB    CLIF_SIGPRO_RM_CONFIG1_REG
+#    A0, 0D, 06, 50, 42, 90, 10, FF, FF    RF_CLIF_CFG_BR_848_I_TXB    CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 06, 50, 4A, 21, 07, 00, 07    RF_CLIF_CFG_BR_848_I_TXB    CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 03, 50, 16, 00                RF_CLIF_CFG_BR_848_I_TXB    CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 50, 15, 00                RF_CLIF_CFG_BR_848_I_TXB    CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 06, 56, 2D, 05, 9E, 0C, 00    RF_CLIF_CFG_BR_212_I_RXF_P  CLIF_SIGPRO_RM_CONFIG1_REG
+#    A0, 0D, 04, 56, 44, 22, 00            RF_CLIF_CFG_BR_212_I_RXF_P  CLIF_ANA_RX_REG
+#    A0, 0D, 06, 5C, 2D, 05, 9E, 0C, 00    RF_CLIF_CFG_BR_424_I_RXF_P  CLIF_SIGPRO_RM_CONFIG1_REG
+#    A0, 0D, 04, 5C, 44, 26, 00            RF_CLIF_CFG_BR_424_I_RXF_P  CLIF_ANA_RX_REG
+#    A0, 0D, 06, 54, 42, 88, 10, FF, FF    RF_CLIF_CFG_BR_212_I_TXF    CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 06, 54, 4A, 33, 07, 01, 07    RF_CLIF_CFG_BR_212_I_TXF    CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 03, 54, 16, 00                RF_CLIF_CFG_BR_212_I_TXF    CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 54, 15, 00                RF_CLIF_CFG_BR_212_I_TXF    CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 06, 5A, 42, 90, 10, FF, FF    RF_CLIF_CFG_BR_424_I_TXF    CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 06, 5A, 4A, 31, 07, 01, 07    RF_CLIF_CFG_BR_424_I_TXF    CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 03, 5A, 16, 00                RF_CLIF_CFG_BR_424_I_TXF    CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 5A, 15, 00                RF_CLIF_CFG_BR_424_I_TXF    CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 06, 98, 2F, CF, 05, 80, 17    RF_CLIF_CFG_GTM_B           CLIF_SIGPRO_ADCBCM_CONFIG_REG
+#    A0, 0D, 06, 98, 42, 00, 02, FF, FF    RF_CLIF_CFG_GTM_B           CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 06, 9A, 42, 00, 02, FF, FF    RF_CLIF_CFG_GTM_FELICA      CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 06, 30, 44, 12, 90, 03, 00    RF_CLIF_CFG_TECHNO_T_RXF    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 6C, 44, A3, 90, 03, 00    RF_CLIF_CFG_BR_106_T_RXA    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 6C, 30, CF, 00, 08, 00    RF_CLIF_CFG_BR_106_T_RXA    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+#    A0, 0D, 06, 6C, 2F, 8F, 05, 80, 0C    RF_CLIF_CFG_BR_106_T_RXA    CLIF_SIGPRO_ADCBCM_CONFIG_REG
+#    A0, 0D, 06, 70, 2F, 8F, 05, 80, 12    RF_CLIF_CFG_BR_212_T_RXA    CLIF_SIGPRO_ADCBCM_CONFIG_REG
+#    A0, 0D, 06, 70, 30, CF, 00, 08, 00    RF_CLIF_CFG_BR_212_T_RXA    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+#    A0, 0D, 03, 70, 2E, 40                RF_CLIF_CFG_BR_212_T_RXA    CLIF_SIGPRO_CM_CONFIG_REG
+#    A0, 0D, 03, 70, 45, 30                RF_CLIF_CFG_BR_212_T_RXA    CLIF_ANA_CM_CONFIG_REG
+#    A0, 0D, 06, 70, 44, A3, 90, 03, 00    RF_CLIF_CFG_BR_212_T_RXA    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 74, 2F, 6F, 05, 80, 12    RF_CLIF_CFG_BR_424_T_RXA    CLIF_SIGPRO_ADCBCM_CONFIG_REG
+#    A0, 0D, 06, 74, 30, D5, 00, 40, 00    RF_CLIF_CFG_BR_424_T_RXA    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+#    A0, 0D, 06, 74, 44, A3, 90, 03, 00    RF_CLIF_CFG_BR_424_T_RXA    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 78, 2F, 3F, 07, 80, C1    RF_CLIF_CFG_BR_848_T_RXA    CLIF_SIGPRO_ADCBCM_CONFIG_REG
+#    A0, 0D, 06, 78, 30, 50, 00, 10, 00    RF_CLIF_CFG_BR_848_T_RXA    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+#    A0, 0D, 06, 78, 44, A3, 90, 03, 00    RF_CLIF_CFG_BR_848_T_RXA    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 7C, 2F, CF, 05, 80, 17    RF_CLIF_CFG_BR_106_T_RXB    CLIF_SIGPRO_ADCBCM_CONFIG_REG
+#    A0, 0D, 06, 7C, 30, C8, 00, 64, 00    RF_CLIF_CFG_BR_106_T_RXB    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+#    A0, 0D, 06, 7C, 44, A3, 90, 03, 00    RF_CLIF_CFG_BR_106_T_RXB    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 80, 2F, CF, 05, 80, 17    RF_CLIF_CFG_BR_212_T_RXB    CLIF_SIGPRO_ADCBCM_CONFIG_REG
+#    A0, 0D, 06, 80, 30, C8, 00, 64, 00    RF_CLIF_CFG_BR_212_T_RXB    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+#    A0, 0D, 06, 80, 44, A3, 90, 03, 00    RF_CLIF_CFG_BR_212_T_RXB    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 84, 2F, CF, 05, 80, 17    RF_CLIF_CFG_BR_424_T_RXB    CLIF_SIGPRO_ADCBCM_CONFIG_REG
+#    A0, 0D, 06, 84, 30, C8, 00, 64, 00    RF_CLIF_CFG_BR_424_T_RXB    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+#    A0, 0D, 06, 84, 44, A3, 90, 03, 00    RF_CLIF_CFG_BR_424_T_RXB    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 88, 2F, B1, 05, 80, 17    RF_CLIF_CFG_BR_848_T_RXB    CLIF_SIGPRO_ADCBCM_CONFIG_REG
+#    A0, 0D, 06, 88, 30, A8, 00, 64, 00    RF_CLIF_CFG_BR_848_T_RXB    CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+#    A0, 0D, 06, 88, 44, A3, 90, 03, 00    RF_CLIF_CFG_BR_848_T_RXB    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 8E, 44, 12, 90, 03, 00    RF_CLIF_CFG_BR_212_T_RXF    CLIF_ANA_RX_REG
+#    A0, 0D, 06, 94, 44, 12, 90, 03, 00    RF_CLIF_CFG_BR_424_T_RXF    CLIF_ANA_RX_REG
+#    A0, 0D, 03, 10, 43, 20                RF_CLIF_CFG_T_ACTIVE        CLIF_ANA_PBF_CONTROL_REG
+#    A0, 0D, 06, 10, 35, FF, 01, FF, 02    RF_CLIF_CFG_T_ACTIVE        CLIF_AGC_INPUT_REG
+#    A0, 0D, 06, 10, 34, F7, 7F, 00, 00    RF_CLIF_CFG_T_ACTIVE        CLIF_AGC_CONFIG1_REG
+#    A0, 0D, 06, 6A, 42, F8, 10, FF, FF    RF_CLIF_CFG_BR_106_T_TXA_A  CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 03, 6A, 16, 00                RF_CLIF_CFG_BR_106_T_TXA_A  CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 6A, 15, 01                RF_CLIF_CFG_BR_106_T_TXA_A  CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 06, 6A, 4A, 30, 0F, 01, 1F    RF_CLIF_CFG_BR_106_T_TXA_A  CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 06, 8C, 42, 88, 10, FF, FF    RF_CLIF_CFG_BR_212_T_TXF_A  CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 06, 8C, 4A, 33, 07, 01, 07    RF_CLIF_CFG_BR_212_T_TXF_A  CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 03, 8C, 16, 00                RF_CLIF_CFG_BR_212_T_TXF_A  CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 8C, 15, 00                RF_CLIF_CFG_BR_212_T_TXF_A  CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 06, 92, 42, 90, 10, FF, FF    RF_CLIF_CFG_BR_424_T_TXF_A  CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 06, 92, 4A, 31, 07, 01, 07    RF_CLIF_CFG_BR_424_T_TXF_A  CLIF_ANA_TX_SHAPE_CONTROL_REG
+#    A0, 0D, 03, 92, 16, 00                RF_CLIF_CFG_BR_424_T_TXF_A  CLIF_TX_UNDERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 92, 15, 00                RF_CLIF_CFG_BR_424_T_TXF_A  CLIF_TX_OVERSHOOT_CONFIG_REG
+#    A0, 0D, 03, 24, 41, 40                RF_CLIF_CFG_TECHNO_T_TXA_P  CLIF_ANA_TX_CLK_CONTROL_REG
+#    A0, 0D, 06, 24, 42, 00, 02, FF, FF    RF_CLIF_CFG_TECHNO_T_TXA_P  CLIF_ANA_TX_AMPLITUDE_REG
+#    A0, 0D, 03, 28, 41, 40                RF_CLIF_CFG_TECHNO_T_TXB    CLIF_ANA_TX_CLK_CONTROL_REG
+#    A0, 0D, 03, 8A, 41, 40                RF_CLIF_CFG_BR_212_T_TXF_P  CLIF_ANA_TX_CLK_CONTROL_REG
+#    A0, 0D, 03, 90, 41, 40                RF_CLIF_CFG_BR_424_T_TXF_P  CLIF_ANA_TX_CLK_CONTROL_REG
+#    A0, 0D, 03, 08, 40, 10                RF_CLIF_CFG_I_PASSIVE       CLIF_ANA_NFCLD_REG
+#    A0, 0D, 06, 08, 45, C0, 82, 00, 00    RF_CLIF_CFG_I_PASSIVE       CLIF_ANA_CM_CONFIG_REG
+#    A0, 0D, 06, 0A, 44, A3, 90, 03, 00    RF_CLIF_CFG_I_ACTIVE        CLIF_ANA_RX_REG
+#    A0, 0D, 06, 0A, 45, 80, 40, 00, 00    RF_CLIF_CFG_I_ACTIVE        CLIF_ANA_CM_CONFIG_REG
+#    A0, 0D, 06, 0A, 30, C8, 00, 64, 00    RF_CLIF_CFG_I_ACTIVE        CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
+#    A0, 0D, 06, 0A, 2F, AF, 05, 80, 17    RF_CLIF_CFG_I_ACTIVE        CLIF_SIGPRO_ADCBCM_CONFIG_REG
+#    A0, 0D, 03, 0A, 48, 10                RF_CLIF_CFG_I_ACTIVE        CLIF_ANA_CLK_MAN_REG
+#    A0, 0D, 06, 0A, 34, 26, 65, E5, 03    RF_CLIF_CFG_I_ACTIVE        CLIF_AGC_CONFIG1_REG
+#    A0, 0D, 06, 0A, 33, 0F, 01, 00, 70    RF_CLIF_CFG_I_ACTIVE        CLIF_AGC_CONFIG0_REG
+#    A0, 0D, 03, 0A, 40, 00                RF_CLIF_CFG_I_ACTIVE        CLIF_ANA_NFCLD_REG
+#
+# *** ALMSL FW VERSION = 10.05.03 ***
+NXP_RF_CONF_BLK_1={
+    20, 02, FA, 20,
+    A0, 0D, 03, 00, 40, 03,
+    A0, 0D, 06, 00, FF, 05, 04, 06, 00,
+    A0, 0D, 06, 00, 35, FF, 01, FF, 02,
+    A0, 0D, 06, 00, 33, 07, 40, 00, 00,
+    A0, 0D, 03, 02, 40, 00,
+    A0, 0D, 03, 04, 43, 20,
+    A0, 0D, 03, 04, 47, 02,
+    A0, 0D, 06, 04, 35, F4, 01, F4, 01,
+    A0, 0D, 06, 04, FF, 05, 00, 00, 00,
+    A0, 0D, 06, 05, 45, 80, 40, 00, 00,
+    A0, 0D, 06, 05, 35, FF, 01, FF, 02,
+    A0, 0D, 06, 05, 33, 07, 40, 00, 00,
+    A0, 0D, 06, 06, 44, A3, 90, 03, 00,
+    A0, 0D, 03, 06, 47, 02,
+    A0, 0D, 06, 06, 35, C0, 03, C0, 02,
+    A0, 0D, 06, 06, 34, F7, 7F, 00, 10,
+    A0, 0D, 06, 06, 33, 03, 40, 00, 00,
+    A0, 0D, 06, 06, 30, B0, 00, 10, 00,
+    A0, 0D, 06, 06, 2F, AF, 05, 80, 17,
+    A0, 0D, 06, 06, 03, 00, 71, 00, 20,
+    A0, 0D, 03, 06, 43, 20,
+    A0, 0D, 06, 06, 42, 00, 03, F2, F2,
+    A0, 0D, 03, 06, 41, 40,
+    A0, 0D, 03, 06, 37, 08,
+    A0, 0D, 03, 06, 16, 00,
+    A0, 0D, 03, 06, 15, 00,
+    A0, 0D, 03, 06, 3F, 04,
+    A0, 0D, 03, 06, 80, 03,
+    A0, 0D, 06, 06, FF, 05, 00, 00, 00,
+    A0, 0D, 03, 07, 3F, 00,
+    A0, 0D, 06, 07, 35, FF, 01, FF, 02,
+    A0, 0D, 06, 07, 33, 07, 40, 00, 00
+}
+
+NXP_RF_CONF_BLK_2={
+    20, 02, F8, 1F,
+    A0, 0D, 06, 18, 34, 00, 00, E1, 03,
+    A0, 0D, 06, 18, 33, 0F, 83, 00, 00,
+    A0, 0D, 06, 1C, 34, 00, 00, E1, 03,
+    A0, 0D, 06, 1C, 33, 0F, 83, 00, 00,
+    A0, 0D, 06, 20, 4A, 00, 00, 00, 00,
+    A0, 0D, 06, 20, 42, 88, 10, FF, FF,
+    A0, 0D, 03, 20, 16, 00,
+    A0, 0D, 03, 20, 15, 00,
+    A0, 0D, 04, 22, 44, 22, 00,
+    A0, 0D, 06, 22, 2D, 50, 44, 0C, 00,
+    A0, 0D, 04, 32, 03, 40, 3D,
+    A0, 0D, 06, 32, 42, F8, 10, FF, FF,
+    A0, 0D, 03, 32, 16, 00,
+    A0, 0D, 03, 32, 15, 01,
+    A0, 0D, 03, 32, 0D, 22,
+    A0, 0D, 03, 32, 14, 22,
+    A0, 0D, 06, 32, 4A, 33, 07, 00, 08,
+    A0, 0D, 06, 34, 2D, 24, 47, 0C, 00,
+    A0, 0D, 06, 34, 34, 00, 00, EC, 03,
+    A0, 0D, 06, 34, 33, 0F, 01, 01, 70,
+    A0, 0D, 04, 34, 44, 21, 00,
+    A0, 0D, 06, 38, 4A, 33, 07, 00, 08,
+    A0, 0D, 06, 38, 42, 68, 10, FF, FF,
+    A0, 0D, 03, 38, 16, 00,
+    A0, 0D, 03, 38, 15, 00,
+    A0, 0D, 04, 3A, 44, 26, 00,
+    A0, 0D, 06, 3A, 2D, 15, 47, 0D, 00,
+    A0, 0D, 06, 3A, 34, 00, 00, E1, 03,
+    A0, 0D, 06, 3A, 33, 0B, 83, 00, 00,
+    A0, 0D, 06, 3C, 4A, 52, 07, 00, 1B,
+    A0, 0D, 06, 3C, 42, 68, 10, FF, FF
+}
+
+NXP_RF_CONF_BLK_3={
+    20, 02, F9, 20,
+    A0, 0D, 03, 3C, 16, 00,
+    A0, 0D, 03, 3C, 15, 00,
+    A0, 0D, 04, 3E, 44, 26, 00,
+    A0, 0D, 06, 3E, 2D, 15, 47, 0D, 00,
+    A0, 0D, 06, 3E, 34, 00, 00, E1, 03,
+    A0, 0D, 06, 3E, 33, 0B, 83, 00, 00,
+    A0, 0D, 06, 40, 42, F0, 10, FF, FF,
+    A0, 0D, 03, 40, 0D, 02,
+    A0, 0D, 03, 40, 14, 02,
+    A0, 0D, 06, 40, 4A, 12, 07, 00, 00,
+    A0, 0D, 03, 40, 16, 00,
+    A0, 0D, 03, 40, 15, 00,
+    A0, 0D, 04, 42, 44, 26, 00,
+    A0, 0D, 06, 42, 2D, 15, 47, 0D, 00,
+    A0, 0D, 06, 42, 34, 00, 00, E1, 03,
+    A0, 0D, 06, 42, 33, 0B, 83, 00, 00,
+    A0, 0D, 04, 46, 44, 26, 00,
+    A0, 0D, 06, 46, 2D, 15, 25, 0D, 00,
+    A0, 0D, 06, 44, 4A, 21, 07, 00, 07,
+    A0, 0D, 06, 44, 42, 88, 10, FF, FF,
+    A0, 0D, 03, 44, 16, 00,
+    A0, 0D, 03, 44, 15, 00,
+    A0, 0D, 04, 4A, 44, 21, 00,
+    A0, 0D, 06, 4A, 2D, 15, 9D, 0D, 00,
+    A0, 0D, 06, 48, 4A, 21, 07, 00, 07,
+    A0, 0D, 06, 48, 42, 88, 10, FF, FF,
+    A0, 0D, 03, 48, 16, 00,
+    A0, 0D, 03, 48, 15, 00,
+    A0, 0D, 04, 4E, 44, 26, 00,
+    A0, 0D, 06, 4E, 2D, 15, 25, 0D, 00,
+    A0, 0D, 06, 4C, 4A, 21, 07, 00, 07,
+    A0, 0D, 06, 4C, 42, 88, 10, FF, FF
+}
+
+NXP_RF_CONF_BLK_4={
+    20, 02, F4, 1F,
+    A0, 0D, 03, 4C, 16, 00,
+    A0, 0D, 03, 4C, 15, 00,
+    A0, 0D, 04, 52, 44, 26, 00,
+    A0, 0D, 06, 52, 2D, 15, 25, 0D, 00,
+    A0, 0D, 06, 50, 42, 90, 10, FF, FF,
+    A0, 0D, 06, 50, 4A, 21, 07, 00, 07,
+    A0, 0D, 03, 50, 16, 00,
+    A0, 0D, 03, 50, 15, 00,
+    A0, 0D, 06, 56, 2D, 05, 9E, 0C, 00,
+    A0, 0D, 04, 56, 44, 22, 00,
+    A0, 0D, 06, 5C, 2D, 05, 9E, 0C, 00,
+    A0, 0D, 04, 5C, 44, 26, 00,
+    A0, 0D, 06, 54, 42, 88, 10, FF, FF,
+    A0, 0D, 06, 54, 4A, 33, 07, 01, 07,
+    A0, 0D, 03, 54, 16, 00,
+    A0, 0D, 03, 54, 15, 00,
+    A0, 0D, 06, 5A, 42, 90, 10, FF, FF,
+    A0, 0D, 06, 5A, 4A, 31, 07, 01, 07,
+    A0, 0D, 03, 5A, 16, 00,
+    A0, 0D, 03, 5A, 15, 00,
+    A0, 0D, 06, 98, 2F, CF, 05, 80, 17,
+    A0, 0D, 06, 98, 42, 00, 03, F2, F2,
+    A0, 0D, 06, 9A, 42, 00, 03, F2, F2,
+    A0, 0D, 06, 30, 44, 12, 90, 03, 00,
+    A0, 0D, 06, 6C, 44, A3, 90, 03, 00,
+    A0, 0D, 06, 6C, 30, CF, 00, 08, 00,
+    A0, 0D, 06, 6C, 2F, 8F, 05, 80, 0C,
+    A0, 0D, 06, 70, 2F, 8F, 05, 80, 12,
+    A0, 0D, 06, 70, 30, CF, 00, 08, 00,
+    A0, 0D, 03, 70, 2E, 40,
+    A0, 0D, 03, 70, 45, 30
+}
+
+NXP_RF_CONF_BLK_5={
+    20, 02, F4, 1C,
+    A0, 0D, 06, 70, 44, A3, 90, 03, 00,
+    A0, 0D, 06, 74, 2F, 6F, 05, 80, 12,
+    A0, 0D, 06, 74, 30, D5, 00, 40, 00,
+    A0, 0D, 06, 74, 44, A3, 90, 03, 00,
+    A0, 0D, 06, 78, 2F, 3F, 07, 80, C1,
+    A0, 0D, 06, 78, 30, 50, 00, 10, 00,
+    A0, 0D, 06, 78, 44, A3, 90, 03, 00,
+    A0, 0D, 06, 7C, 2F, CF, 05, 80, 17,
+    A0, 0D, 06, 7C, 30, B0, 00, 10, 00,
+    A0, 0D, 06, 7C, 44, A3, 90, 03, 00,
+    A0, 0D, 06, 80, 2F, CF, 05, 80, 17,
+    A0, 0D, 06, 80, 30, C8, 00, 64, 00,
+    A0, 0D, 06, 80, 44, A3, 90, 03, 00,
+    A0, 0D, 06, 84, 2F, CF, 05, 80, 17,
+    A0, 0D, 06, 84, 30, C8, 00, 64, 00,
+    A0, 0D, 06, 84, 44, A3, 90, 03, 00,
+    A0, 0D, 06, 88, 2F, B1, 05, 80, 17,
+    A0, 0D, 06, 88, 30, A8, 00, 64, 00,
+    A0, 0D, 06, 88, 44, A3, 90, 03, 00,
+    A0, 0D, 06, 8E, 44, 12, 90, 03, 00,
+    A0, 0D, 06, 94, 44, 12, 90, 03, 00,
+    A0, 0D, 03, 10, 43, 20,
+    A0, 0D, 06, 10, 35, FF, 01, FF, 02,
+    A0, 0D, 06, 10, 34, F7, 7F, 00, 00,
+    A0, 0D, 06, 6A, 42, F8, 10, FF, FF,
+    A0, 0D, 03, 6A, 16, 00,
+    A0, 0D, 03, 6A, 15, 01,
+    A0, 0D, 06, 6A, 4A, 30, 0F, 01, 1F
+}
+
+NXP_RF_CONF_BLK_6={
+    20, 02, AF, 17,
+    A0, 0D, 06, 8C, 42, 88, 10, FF, FF,
+    A0, 0D, 06, 8C, 4A, 33, 07, 01, 07,
+    A0, 0D, 03, 8C, 16, 00,
+    A0, 0D, 03, 8C, 15, 00,
+    A0, 0D, 06, 92, 42, 90, 10, FF, FF,
+    A0, 0D, 06, 92, 4A, 31, 07, 01, 07,
+    A0, 0D, 03, 92, 16, 00,
+    A0, 0D, 03, 92, 15, 00,
+    A0, 0D, 03, 24, 41, 40,
+    A0, 0D, 06, 24, 42, 00, 03, F2, F2,
+    A0, 0D, 03, 28, 41, 40,
+    A0, 0D, 03, 8A, 41, 40,
+    A0, 0D, 03, 90, 41, 40,
+    A0, 0D, 03, 08, 40, 10,
+    A0, 0D, 06, 08, 45, C0, 82, 00, 00,
+    A0, 0D, 06, 0A, 44, A3, 90, 03, 00,
+    A0, 0D, 06, 0A, 45, 80, 40, 00, 00,
+    A0, 0D, 06, 0A, 30, C8, 00, 64, 00,
+    A0, 0D, 06, 0A, 2F, AF, 05, 80, 17,
+    A0, 0D, 03, 0A, 48, 10,
+    A0, 0D, 06, 0A, 34, 26, 65, E5, 03,
+    A0, 0D, 06, 0A, 33, 0F, 01, 00, 70,
+    A0, 0D, 03, 0A, 40, 00
+}
+
+
+###############################################################################
+
+
+
+
+###############################################################################
+# Core configuration extensions
+# It includes
+# A002      - Disable/Enable Clock Request
+# A009      - Time-out before standby
+# A012      - NFCEE interface 2 configuration
+# A040      - Low Power Card Detector Enable
+# A041      - Low Power Card Detector Threshold
+# A042      - Low Power Card Detector Sampling
+# A043      - Low Power Card Detector Hybrid
+# A05E      - Send RID automatically in Jewel Reader mode
+# A061      - Retry after LPCD
+# A096      - Notify all AIDs
+# A0DD      - Retry on SWP2 interface
+# A0EC      - Disable/Enable SWP1 interface
+# A0ED      - Disable/Enable SWP2 interface
+# A0F2      - SVDD_PWR_REQ enable
+NXP_CORE_CONF_EXTN={20, 02, B3, 13,
+        A0, 02, 01, 01,
+        A0, 09, 02, E8, 03,
+        A0, 12, 01, 00,
+        A0, 40, 01, 01,
+        A0, 41, 01, 05,
+        A0, 42, 01, 0F,
+        A0, 43, 01, 03,
+        A0, 5E, 01, 01,
+        A0, 61, 01, 53,
+        A0, 96, 01, 01,
+        A0, DD, 01, 2D,
+        A0, EC, 01, 01,
+        A0, ED, 01, 00,
+        A0, F2, 01, 00,
+        A0, 47, 02, 00, 32,
+        A0, D5, 01, 04,
+        A0, 1D, 11, 51, 33, 14, 17, 00, AA, 85, 00, 80, 55, 2A, 04, 00, 63, 00, 00, 00,
+        A0, 1E, 11, 1B, 13, 14, 14, 00, 6F, 97, 00, 00, 00, 10, 04, 00, 63, 02, 00, 00,
+        A0, 92, 45, 23, 04, 50, 10, 00, 00, 00, 14, 00, 20, 00, 14, 00, B3, 00, 06, 00, 20, 01, 06, 00, FF, 03, 06, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00
+}
+
+
+###############################################################################
+# Core configuration extensions
+# It includes
+# A002      - Disable/Enable Clock Request
+# A009      - Time-out before standby
+# A012      - NFCEE interface 2 configuration
+# A040      - Low Power Card Detector Enable
+# A041      - Low Power Card Detector Threshold
+# A042      - Low Power Card Detector Sampling
+# A043      - Low Power Card Detector Hybrid
+# A05E      - Send RID automatically in Jewel Reader mode
+# A061      - Retry after LPCD
+# A096      - Notify all AIDs
+# A0DD      - Retry on SWP2 interface
+# A0EC      - Disable/Enable SWP1 interface
+# A0ED      - Disable/Enable SWP2 interface
+# A0F2      - SVDD_PWR_REQ enable
+NXP_CORE_CONF_EXTN={20, 02, B7, 14,
+        A0, 02, 01, 01,
+        A0, 09, 02, E8, 03,
+        A0, 12, 01, 00,
+        A0, 40, 01, 01,
+        A0, 41, 01, 05,
+        A0, 42, 01, 0F,
+        A0, 43, 01, 03,
+        A0, 5E, 01, 01,
+        A0, 61, 01, 53,
+        A0, 96, 01, 01,
+        A0, DD, 01, 2D,
+        A0, EC, 01, 01,
+        A0, ED, 01, 00,
+        A0, F2, 01, 00,
+        A0, 47, 02, 00, 27,
+        A0, CD, 01, 1F,
+        A0, CB, 01, 10,
+        A0, 1D, 11, 52, 33, 14, 17, 00, AA, 85, 00, 80, 55, 2A, 04, 00, 63, 00, 00, 00,
+        A0, 1E, 11, 1B, 13, 14, 14, 00, 6F, 97, 00, 00, 00, 10, 04, 00, 63, 02, 00, 00,
+        A0, 92, 45, 23, 04, 50, 10, 00, 00, 00, 14, 00, 20, 00, 14, 00, B3, 00, 06, 00, 20, 01, 06, 00, FF, 03, 06, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00
+        }
+
+
+###############################################################################
+# Core configuration settings
+# It includes
+# 18        - Poll Mode NFC-F:   PF_BIT_RATE
+# 21        - Poll Mode ISO-DEP: PI_BIT_RATE
+# 28        - Poll Mode NFC-DEP: PN_NFC_DEP_SPEED
+# 30        - Lis. Mode NFC-A:   LA_BIT_FRAME_SDD
+# 31        - Lis. Mode NFC-A:   LA_PLATFORM_CONFIG
+# 33        - Lis. Mode NFC-A:   LA_NFCID1
+# 50        - Lis. Mode NFC-F:   LF_PROTOCOL_TYPE
+# 54        - Lis. Mode NFC-F:   LF_CON_BITR_F
+# 5B        - Lis. Mode ISO-DEP: LI_BIT_RATE
+# 60        - Lis. Mode NFC-DEP: LN_WT
+# 80        - Other Param.:      RF_FIELD_INFO
+# 81        - Other Param.:      RF_NFCEE_ACTION
+# 82        - Other Param.:      NFCDEP_OP
+NXP_CORE_CONF={20, 02, 2A, 0E,
+        18, 01, 01,
+        21, 01, 00,
+        28, 01, 00,
+        30, 01, 04,
+        31, 01, 00,
+        33, 00,
+        50, 01, 02,
+        54, 01, 06,
+        5B, 01, 00,
+        60, 01, 0E,
+        80, 01, 01,
+        81, 01, 01,
+        82, 01, 0E,
+        32, 01, 60
+        }
--- a/phh-on-data.sh
+++ b/phh-on-data.sh
@ -9,10 +9,33 @@ if getprop persist.sys.phh.no_vendor_overlay |grep -q true;then
 	done
 fi

+if getprop persist.sys.phh.no_stock_apps |grep -q true; then
+	for part in odm vendor; do
+		mount /mnt/phh/empty_dir/ /$part/overlay
+		mount /mnt/phh/empty_dir/ /$part/app
+	done
+fi
+
 if getprop persist.sys.phh.caf.media_profile |grep -q true; then
    setprop media.settings.xml "/vendor/etc/media_profiles_vendor.xml"
 fi

+# Add persist props for Redmi Note 9S/Pro/Max
+if getprop ro.vendor.build.fingerprint |grep -iq -e redmi/curtana \
+  -e redmi/joyeuse -e redmi/excalibur; then
+    setprop persist.sys.phh.disable_audio_effects 1
+    setprop persist.sys.phh.disable_a2dp_offload true
+    setprop persist.bluetooth.bluetooth_audio_hal.disabled true
+    setprop persist.sys.phh.caf.audio_policy 1
+    mount -o bind /system/etc/mixer_paths_wcd937x.xml /vendor/etc/mixer_paths_wcd937x.xml
+    mount -o bind /system/etc/media_profiles_vendor.xml /vendor/etc/media_profiles_vendor.xml
+    setprop ctl.restart vendor.audio-hal-2-0
+    setprop persist.sys.phh.linear_brightness false
+    setprop persist.sys.phh.backlight.scale 1
+    setprop persist.sys.phh.caf.media_profile true
+    setprop persist.sys.overlay.minimal_brightness true
+    pkill -f com.android.bluetooth
+fi

 minijailSrc=/system/system_ext/apex/com.android.vndk.v28/lib/libminijail.so
 minijailSrc64=/system/system_ext/apex/com.android.vndk.v28/lib64/libminijail.so
--- a/phh-prop-handler.sh
+++ b/phh-prop-handler.sh
@ -195,6 +195,119 @@ if [ "$1" == "persist.sys.phh.backlight.scale" ];then
    exit
 fi

+if [ "$1" == "persist.sys.phh.qin.dt2w" ];then
+    if [[ "$prop_value" != "0" && "$prop_value" != "1" ]]; then
+        exit 1
+    fi
+
+    echo "$prop_value" > /sys/devices/platform/soc/soc:ap-apb/70800000.i2c/i2c-3/3-0038/fts_gesture_mode
+    exit
+fi
+
+#root
+if [ "$1" == "persist.sys.phh.root" ]; then
+    if [[ "$prop_value" != "false" && "$prop_value" != "true" ]] || [ -d /sbin/.magisk ]; then
+        exit 1
+    fi
+
+    if [[ "$prop_value" == "true" ]]; then
+        umount -nfl /system/xbin
+        cp -r --preserve=all /system/xbin /mnt/phh/xbin
+        cp --preserve=all /system/phh/xbin/* /mnt/phh/xbin
+        mount /mnt/phh/xbin /system/xbin
+        setprop ctl.start zerodaemon
+        pm install -r /system/phh/phh.superuser.apk
+    else
+        pm uninstall -k me.phh.superuser
+        setprop ctl.stop zerodaemon
+        umount -nfl /system/xbin
+        rm -rf /mnt/phh/xbin /data/su
+    fi
+    exit
+fi
+
+#safetynet
+if [ "$1" == "persist.sys.phh.safetynet" ]; then
+    if [[ "$prop_value" != "true" ]]; then
+        exit 1
+    fi
+
+    if [ ! -f /data/adb/phh/secure ]; then
+        mkdir -p /data/adb/phh
+        cp /system/phh/secure.sh /data/adb/phh/secure
+    fi
+    /system/bin/sh /data/adb/phh/secure
+    exit
+fi
+
+#pixel5props
+if [ "$1" == "persist.sys.phh.pixelprops" ]; then
+    if [[ "$prop_value" != "true" ]]; then
+        exit 1
+    fi
+
+    if [ -f /data/adb/phh/secure ] && grep xxx /data/adb/phh/secure; then
+        sed -i '1,3d' /data/adb/phh/secure
+    fi
+    exit
+fi
+
+#autorun
+if [ "$1" == "persist.sys.phh.autorun" ]; then
+    if [[ "$prop_value" != "true" ]]; then
+        exit 1
+    fi
+
+    if [ ! -f /data/adb/phh/run ]; then
+        mkdir -p /data/adb/phh
+        touch /data/adb/phh/run
+    fi
+    /system/bin/sh /data/adb/phh/run
+    exit
+fi
+
+#nolog
+if [ "$1" == "persist.sys.phh.nolog" ]; then
+    if [[ "$prop_value" != "false" && "$prop_value" != "true" ]]; then
+        exit 1
+    fi
+
+    if [[ "$prop_value" == "true" ]]; then
+        setprop ctl.stop logd
+        setprop ctl.stop traced
+        setprop ctl.stop traced_probes
+    else
+        setprop ctl.start traced_probes
+        setprop ctl.start traced
+        setprop ctl.start logd
+    fi
+    exit
+fi
+
+#restart_sysui
+if [ "$1" == "sys.phh.restart_sysui" ]; then
+    if [[ "$prop_value" = "false" && "$prop_value" != "true" ]]; then
+        exit
+    fi
+
+    if [[ "$prop_value" == "true" ]]; then
+        pkill systemui
+    fi
+    exit
+fi
+
+#dump_logs
+if [ "$1" == "sys.phh.dump_logs" ]; then
+    if [[ "$prop_value" = "false" && "$prop_value" != "true" ]]; then
+        exit
+    fi
+
+    if [[ "$prop_value" == "true" ]]; then
+        logcat -b all -d > /sdcard/logs.txt
+    fi
+    exit
+fi
+
 if [ "$1" == "persist.sys.phh.disable_soundvolume_effect" ];then
    if [[ "$prop_value" != "0" && "$prop_value" != "1" ]]; then
        exit 1
--- a/phh.mk
+++ b/phh.mk
--- a/phh.superuser.apk
+++ b/phh.superuser.apk
--- a/rw-system.sh
+++ b/rw-system.sh
@ -587,16 +587,9 @@ if getprop ro.vendor.build.fingerprint | grep -iq -e Redmi/rosemary \
    setprop debug.sf.enable_hwc_vds 0
 fi

+
 if getprop ro.vendor.build.fingerprint | grep -iq -E -e 'huawei|honor' || getprop persist.sys.overlay.huawei | grep -iq -E -e 'true'; then
-    p=/product/etc/nfc/libnfc_nxp_*_*.conf
-    mount -o bind "$p" /system/etc/libnfc-nxp.conf ||
-        mount -o bind /product/etc/libnfc-nxp.conf /system/etc/libnfc-nxp.conf || true
-
-    p=/product/etc/nfc/libnfc_brcm_*_*.conf
-    mount -o bind "$p" /system/etc/libnfc-brcm.conf ||
-        mount -o bind /product/etc/libnfc-nxp.conf /system/etc/libnfc-nxp.conf || true
-
-    mount -o bind /system/phh/libnfc-nci-huawei.conf /system/etc/libnfc-nci.conf
+	# Remove NFC link to allow copy nfc files in build
 fi

 if getprop ro.vendor.build.fingerprint | grep -qE -e ".*(crown|star)[q2]*lte.*" -e ".*(SC-0[23]K|SCV3[89]).*" && [ "$vndk" -lt 28 ]; then
--- a/secure.sh
+++ b/secure.sh
@ -0,0 +1,16 @@
+(getprop ro.vendor.build.security_patch; getprop ro.keymaster.xxx.security_patch) |sort |tail -n 1 |while read v;do
+    [ -n "$v" ] && resetprop_phh ro.build.version.security_patch "$v"
+done
+resetprop_phh ro.build.tags release-keys
+resetprop_phh ro.boot.vbmeta.device_state locked
+resetprop_phh ro.boot.verifiedbootstate green
+resetprop_phh ro.boot.flash.locked 1
+resetprop_phh ro.boot.veritymode enforcing
+resetprop_phh ro.boot.warranty_bit 0
+resetprop_phh ro.warranty_bit 0
+resetprop_phh ro.debuggable 0
+resetprop_phh ro.secure 1
+resetprop_phh ro.build.type user
+resetprop_phh ro.build.selinux 0
+resetprop_phh ro.adb.secure 1
+setprop ctl.restart adbd
--- a/sepolicy/file_contexts
+++ b/sepolicy/file_contexts
@ -1,4 +1,5 @@
 /system/bin/phh-su                   u:object_r:phhsu_exec:s0
+/system/bin/zerodaemon               u:object_r:phhsu_exec:s0
 /system/bin/vndk-detect			u:object_r:vndk_detect_exec:s0
 /system/etc/usb_audio_policy_configuration.xml	u:object_r:vendor_configs_file:s0
 /system/bin/rw-system.sh u:object_r:phhsu_exec:s0
--- a/sepolicy/gsicharger.te
+++ b/sepolicy/gsicharger.te
@ -0,0 +1 @@
+permissive charger;
--- a/vndk.rc
+++ b/vndk.rc
@ -53,6 +53,9 @@ on property:persist.sys.phh.disable_soundvolume_effect=*
 on property:ro.sf.lcd_density=*
    restart surfaceflinger

+on property:persist.sys.phh.qin.dt2w=*
+    exec u:r:phhsu_daemon:s0 root -- /system/bin/phh-prop-handler.sh "persist.sys.phh.qin.dt2w"
+
 on property:persist.sys.phh.disable_a2dp_offload=0
    setprop persist.sys.phh.disable_a2dp_offload false

@ -62,6 +65,27 @@ on property:persist.sys.phh.disable_a2dp_offload=1
 on property:persist.sys.phh.disable_a2dp_offload=*
    setprop persist.bluetooth.bluetooth_audio_hal.disabled ${persist.sys.phh.disable_a2dp_offload}

+on property:persist.sys.phh.root=*
+    exec u:r:phhsu_daemon:s0 root -- /system/bin/phh-prop-handler.sh "persist.sys.phh.root"
+
+on property:persist.sys.phh.safetynet=*
+    exec u:r:phhsu_daemon:s0 root -- /system/bin/phh-prop-handler.sh "persist.sys.phh.safetynet"
+
+on property:persist.sys.phh.pixelprops=*
+    exec u:r:phhsu_daemon:s0 root -- /system/bin/phh-prop-handler.sh "persist.sys.phh.pixelprops"
+
+on property:persist.sys.phh.autorun=*
+    exec u:r:phhsu_daemon:s0 root -- /system/bin/phh-prop-handler.sh "persist.sys.phh.autorun"
+
+on property:persist.sys.phh.nolog=*
+    exec u:r:phhsu_daemon:s0 root -- /system/bin/phh-prop-handler.sh "persist.sys.phh.nolog"
+
+on property:sys.phh.restart_sysui=*
+    exec u:r:phhsu_daemon:s0 root -- /system/bin/phh-prop-handler.sh "sys.phh.restart_sysui"
+
+on property:sys.phh.dump_logs=*
+    exec u:r:phhsu_daemon:s0 root -- /system/bin/phh-prop-handler.sh "sys.phh.dump_logs"
+
 on property:init.svc.ril-proxy=stopped && property:persist.sys.phh.restart_ril=true
    start ril-proxy

--- a/zerodaemon/Android.mk
+++ b/zerodaemon/Android.mk
@ -0,0 +1,11 @@
+LOCAL_PATH := $(call my-dir)
+
+include $(CLEAR_VARS)
+
+LOCAL_SRC_FILES := zerodaemon
+LOCAL_MODULE := zerodaemon
+LOCAL_MODULE_CLASS := EXECUTABLES
+
+LOCAL_INIT_RC := zerodaemon.rc
+
+include $(BUILD_PREBUILT)
--- a/zerodaemon/zerodaemon
+++ b/zerodaemon/zerodaemon
--- a/zerodaemon/zerodaemon.rc
+++ b/zerodaemon/zerodaemon.rc
@ -0,0 +1,3 @@
+service zerodaemon /system/bin/zerodaemon --daemon
+    class main
+    disabled
Author	SHA1	Message	Date
Victor Bo	49ae7b2188	add offline charger sepolicy	2022-09-21 15:45:32 +02:00
Andy CrossGate Yan	a1b79d1442	treble: Set TARGET_NO_KERNEL_OVERRIDE Taken from Lineage generic targets - skips building kernel cleanly Change-Id: Id71d3a3aed56fd4e815a64ef4191b125fc5026ce	2022-09-21 15:45:30 +02:00
Andy CrossGate Yan	4b99fc091b	treble: Set BOARD_EXT4_SHARE_DUP_BLOCKS explicitly Change-Id: I725443154fabde548d2e6c1b072d34c27596c421	2022-09-21 15:45:27 +02:00
Raphael Mounier	1a0cc80ebd	Add several new functions from eremitein and remove Huawei NFC Add several new functions : - Add dynamic root option - Add safetynet - Add Pixel5 Prop spoof - Add Autorun - Add NoLog - Add Restart sysui - Add Dump Logs - Add Disable Sound Volume Effect - Add BusyBox link Remove link to NFC file for Huawei device	2022-09-21 15:45:19 +02:00