503 lines
28 KiB
Plaintext
Executable File
503 lines
28 KiB
Plaintext
Executable File
###############################################################################
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# NXP RF ALMSL configuration settings for FW VERSION = 10.05.03
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#
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# A0, 0D, 03, 00, 40, 01 RF_CLIF_CFG_BOOT CLIF_ANA_NFCLD_REG
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# A0, 0D, 06, 00, FF, 05, 04, 06, 00 RF_CLIF_CFG_BOOT SMU_PMU_REG (0x40024010)
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# A0, 0D, 06, 00, 35, FF, 01, FF, 02 RF_CLIF_CFG_BOOT CLIF_AGC_INPUT_REG
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# A0, 0D, 06, 00, 33, 07, 40, 00, 00 RF_CLIF_CFG_BOOT CLIF_AGC_CONFIG0_REG
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# A0, 0D, 03, 02, 40, 00 RF_CLIF_CFG_IDLE CLIF_ANA_NFCLD_REG
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# A0, 0D, 03, 04, 43, 20 RF_CLIF_CFG_INITIATOR CLIF_ANA_PBF_CONTROL_REG
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# A0, 0D, 03, 04, 47, 02 RF_CLIF_CFG_INITIATOR CLIF_ANA_AGC_REG
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# A0, 0D, 06, 04, 35, F4, 01, F4, 01 RF_CLIF_CFG_INITIATOR CLIF_AGC_INPUT_REG
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# A0, 0D, 06, 04, FF, 05, 00, 00, 00 RF_CLIF_CFG_INITIATOR SMU_PMU_REG (0x40024010)
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# A0, 0D, 06, 05, 45, 80, 40, 00, 00 RF_CLIF_CFG_INITIATOR CLIF_ANA_CM_CONFIG_REG
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# A0, 0D, 06, 05, 35, FF, 01, FF, 02 RF_CLIF_CFG_INITIATOR CLIF_AGC_INPUT_REG
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# A0, 0D, 06, 05, 33, 07, 40, 00, 00 RF_CLIF_CFG_INITIATOR CLIF_AGC_CONFIG0_REG
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# A0, 0D, 06, 06, 44, A3, 90, 03, 00 RF_CLIF_CFG_TARGET CLIF_ANA_RX_REG
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# A0, 0D, 03, 06, 47, 02 RF_CLIF_CFG_TARGET CLIF_ANA_AGC_REG
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# A0, 0D, 06, 06, 35, FF, 03, FF, 03 RF_CLIF_CFG_TARGET CLIF_AGC_INPUT_REG
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# A0, 0D, 06, 06, 34, F7, 7F, 00, 10 RF_CLIF_CFG_TARGET CLIF_AGC_CONFIG1_REG
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# A0, 0D, 06, 06, 33, 03, 40, 00, 00 RF_CLIF_CFG_TARGET CLIF_AGC_CONFIG0_REG
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# A0, 0D, 06, 06, 30, C8, 00, 64, 00 RF_CLIF_CFG_TARGET CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
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# A0, 0D, 06, 06, 2F, AF, 05, 80, 17 RF_CLIF_CFG_TARGET CLIF_SIGPRO_ADCBCM_CONFIG_REG
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# A0, 0D, 06, 06, 03, 00, 6D, 00, 20 RF_CLIF_CFG_TARGET CLIF_TRANSCEIVE_CONTROL_REG
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# A0, 0D, 03, 06, 43, 20 RF_CLIF_CFG_TARGET CLIF_ANA_PBF_CONTROL_REG
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# A0, 0D, 06, 06, 42, 00, 02, FF, FF RF_CLIF_CFG_TARGET CLIF_ANA_TX_AMPLITUDE_REG
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# A0, 0D, 03, 06, 41, 40 RF_CLIF_CFG_TARGET CLIF_ANA_TX_CLK_CONTROL_REG
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# A0, 0D, 03, 06, 37, 08 RF_CLIF_CFG_TARGET CLIF_TX_CONTROL_REG
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# A0, 0D, 03, 06, 16, 00 RF_CLIF_CFG_TARGET CLIF_TX_UNDERSHOOT_CONFIG_REG
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# A0, 0D, 03, 06, 15, 00 RF_CLIF_CFG_TARGET CLIF_TX_OVERSHOOT_CONFIG_REG
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# A0, 0D, 03, 06, 3F, 04 RF_CLIF_CFG_TARGET CLIF_TEST_CONTROL_REG
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# A0, 0D, 03, 06, 80, 03 RF_CLIF_CFG_TARGET CLIF_SPARE_REG
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# A0, 0D, 06, 06, FF, 05, 00, 00, 00 RF_CLIF_CFG_TARGET SMU_PMU_REG (0x40024010)
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# A0, 0D, 03, 07, 3F, 00 RF_CLIF_CFG_TARGET CLIF_TEST_CONTROL_REG
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# A0, 0D, 06, 07, 35, FF, 01, FF, 02 RF_CLIF_CFG_TARGET CLIF_AGC_INPUT_REG
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# A0, 0D, 06, 07, 33, 07, 40, 00, 00 RF_CLIF_CFG_TARGET CLIF_AGC_CONFIG0_REG
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# A0, 0D, 06, 18, 34, 00, 00, E1, 03 RF_CLIF_CFG_TECHNO_I_RXB CLIF_AGC_CONFIG1_REG
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# A0, 0D, 06, 18, 33, 0F, 83, 00, 00 RF_CLIF_CFG_TECHNO_I_RXB CLIF_AGC_CONFIG0_REG
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# A0, 0D, 06, 1C, 34, 00, 00, E1, 03 RF_CLIF_CFG_TECHNO_I_RXF_P CLIF_AGC_CONFIG1_REG
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# A0, 0D, 06, 1C, 33, 0F, 83, 00, 00 RF_CLIF_CFG_TECHNO_I_RXF_P CLIF_AGC_CONFIG0_REG
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# A0, 0D, 06, 20, 4A, 00, 00, 00, 00 RF_CLIF_CFG_TECHNO_I_TX15693CLIF_ANA_TX_SHAPE_CONTROL_REG
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# A0, 0D, 06, 20, 42, 88, 10, FF, FF RF_CLIF_CFG_TECHNO_I_TX15693CLIF_ANA_TX_AMPLITUDE_REG
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# A0, 0D, 03, 20, 16, 00 RF_CLIF_CFG_TECHNO_I_TX15693CLIF_TX_UNDERSHOOT_CONFIG_REG
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# A0, 0D, 03, 20, 15, 00 RF_CLIF_CFG_TECHNO_I_TX15693CLIF_TX_OVERSHOOT_CONFIG_REG
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# A0, 0D, 04, 22, 44, 22, 00 RF_CLIF_CFG_TECHNO_I_RX15693CLIF_ANA_RX_REG
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# A0, 0D, 06, 22, 2D, 50, 44, 0C, 00 RF_CLIF_CFG_TECHNO_I_RX15693CLIF_SIGPRO_RM_CONFIG1_REG
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# A0, 0D, 04, 32, 03, 40, 3D RF_CLIF_CFG_BR_106_I_TXA CLIF_TRANSCEIVE_CONTROL_REG
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# A0, 0D, 06, 32, 42, F8, 10, FF, FF RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
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# A0, 0D, 03, 32, 16, 00 RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
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# A0, 0D, 03, 32, 15, 01 RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
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# A0, 0D, 03, 32, 0D, 22 RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_DATA_MOD_REG
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# A0, 0D, 03, 32, 14, 22 RF_CLIF_CFG_BR_106_I_TXA CLIF_TX_SYMBOL23_MOD_REG
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# A0, 0D, 06, 32, 4A, 33, 07, 00, 08 RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
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# A0, 0D, 06, 34, 2D, 24, 47, 0C, 00 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_SIGPRO_RM_CONFIG1_REG
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# A0, 0D, 06, 34, 34, 00, 00, EC, 03 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_AGC_CONFIG1_REG
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# A0, 0D, 06, 34, 33, 0F, 01, 01, 70 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_AGC_CONFIG0_REG
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# A0, 0D, 04, 34, 44, 21, 00 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_ANA_RX_REG
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# A0, 0D, 06, 38, 4A, 33, 07, 00, 08 RF_CLIF_CFG_BR_212_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
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# A0, 0D, 06, 38, 42, 68, 10, FF, FF RF_CLIF_CFG_BR_212_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
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# A0, 0D, 03, 38, 16, 00 RF_CLIF_CFG_BR_212_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
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# A0, 0D, 03, 38, 15, 00 RF_CLIF_CFG_BR_212_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
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# A0, 0D, 04, 3A, 44, 26, 00 RF_CLIF_CFG_BR_212_I_RXA CLIF_ANA_RX_REG
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# A0, 0D, 06, 3A, 2D, 15, 47, 0D, 00 RF_CLIF_CFG_BR_212_I_RXA CLIF_SIGPRO_RM_CONFIG1_REG
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# A0, 0D, 06, 3A, 34, 00, 00, E1, 03 RF_CLIF_CFG_BR_212_I_RXA CLIF_AGC_CONFIG1_REG
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# A0, 0D, 06, 3A, 33, 0B, 83, 00, 00 RF_CLIF_CFG_BR_212_I_RXA CLIF_AGC_CONFIG0_REG
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# A0, 0D, 06, 3C, 4A, 52, 07, 00, 1B RF_CLIF_CFG_BR_424_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
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# A0, 0D, 06, 3C, 42, 68, 10, FF, FF RF_CLIF_CFG_BR_424_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
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# A0, 0D, 03, 3C, 16, 00 RF_CLIF_CFG_BR_424_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
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# A0, 0D, 03, 3C, 15, 00 RF_CLIF_CFG_BR_424_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
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# A0, 0D, 04, 3E, 44, 26, 00 RF_CLIF_CFG_BR_424_I_RXA CLIF_ANA_RX_REG
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# A0, 0D, 06, 3E, 2D, 15, 47, 0D, 00 RF_CLIF_CFG_BR_424_I_RXA CLIF_SIGPRO_RM_CONFIG1_REG
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# A0, 0D, 06, 3E, 34, 00, 00, E1, 03 RF_CLIF_CFG_BR_424_I_RXA CLIF_AGC_CONFIG1_REG
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# A0, 0D, 06, 3E, 33, 0B, 83, 00, 00 RF_CLIF_CFG_BR_424_I_RXA CLIF_AGC_CONFIG0_REG
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# A0, 0D, 06, 40, 42, F0, 10, FF, FF RF_CLIF_CFG_BR_848_I_TXA CLIF_ANA_TX_AMPLITUDE_REG
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# A0, 0D, 03, 40, 0D, 02 RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_DATA_MOD_REG
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# A0, 0D, 03, 40, 14, 02 RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_SYMBOL23_MOD_REG
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# A0, 0D, 06, 40, 4A, 12, 07, 00, 00 RF_CLIF_CFG_BR_848_I_TXA CLIF_ANA_TX_SHAPE_CONTROL_REG
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# A0, 0D, 03, 40, 16, 00 RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_UNDERSHOOT_CONFIG_REG
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# A0, 0D, 03, 40, 15, 00 RF_CLIF_CFG_BR_848_I_TXA CLIF_TX_OVERSHOOT_CONFIG_REG
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# A0, 0D, 04, 42, 44, 26, 00 RF_CLIF_CFG_BR_848_I_RXA CLIF_ANA_RX_REG
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# A0, 0D, 06, 42, 2D, 15, 47, 0D, 00 RF_CLIF_CFG_BR_848_I_RXA CLIF_SIGPRO_RM_CONFIG1_REG
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# A0, 0D, 06, 42, 34, 00, 00, E1, 03 RF_CLIF_CFG_BR_848_I_RXA CLIF_AGC_CONFIG1_REG
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# A0, 0D, 06, 42, 33, 0B, 83, 00, 00 RF_CLIF_CFG_BR_848_I_RXA CLIF_AGC_CONFIG0_REG
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# A0, 0D, 04, 46, 44, 26, 00 RF_CLIF_CFG_BR_106_I_RXB CLIF_ANA_RX_REG
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# A0, 0D, 06, 46, 2D, 15, 25, 0D, 00 RF_CLIF_CFG_BR_106_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
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# A0, 0D, 06, 44, 4A, 21, 07, 00, 07 RF_CLIF_CFG_BR_106_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG
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# A0, 0D, 06, 44, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_106_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
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# A0, 0D, 03, 44, 16, 00 RF_CLIF_CFG_BR_106_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
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# A0, 0D, 03, 44, 15, 00 RF_CLIF_CFG_BR_106_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG
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# A0, 0D, 04, 4A, 44, 21, 00 RF_CLIF_CFG_BR_212_I_RXB CLIF_ANA_RX_REG
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# A0, 0D, 06, 4A, 2D, 15, 9D, 0D, 00 RF_CLIF_CFG_BR_212_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
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# A0, 0D, 06, 48, 4A, 21, 07, 00, 07 RF_CLIF_CFG_BR_212_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG
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# A0, 0D, 06, 48, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_212_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
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# A0, 0D, 03, 48, 16, 00 RF_CLIF_CFG_BR_212_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
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# A0, 0D, 03, 48, 15, 00 RF_CLIF_CFG_BR_212_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG
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# A0, 0D, 04, 4E, 44, 26, 00 RF_CLIF_CFG_BR_424_I_RXB CLIF_ANA_RX_REG
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# A0, 0D, 06, 4E, 2D, 15, 25, 0D, 00 RF_CLIF_CFG_BR_424_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
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# A0, 0D, 06, 4C, 4A, 21, 07, 00, 07 RF_CLIF_CFG_BR_424_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG
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# A0, 0D, 06, 4C, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_424_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
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# A0, 0D, 03, 4C, 16, 00 RF_CLIF_CFG_BR_424_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
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# A0, 0D, 03, 4C, 15, 00 RF_CLIF_CFG_BR_424_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG
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# A0, 0D, 04, 52, 44, 26, 00 RF_CLIF_CFG_BR_848_I_RXB CLIF_ANA_RX_REG
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# A0, 0D, 06, 52, 2D, 15, 25, 0D, 00 RF_CLIF_CFG_BR_848_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG
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# A0, 0D, 06, 50, 42, 90, 10, FF, FF RF_CLIF_CFG_BR_848_I_TXB CLIF_ANA_TX_AMPLITUDE_REG
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# A0, 0D, 06, 50, 4A, 21, 07, 00, 07 RF_CLIF_CFG_BR_848_I_TXB CLIF_ANA_TX_SHAPE_CONTROL_REG
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# A0, 0D, 03, 50, 16, 00 RF_CLIF_CFG_BR_848_I_TXB CLIF_TX_UNDERSHOOT_CONFIG_REG
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# A0, 0D, 03, 50, 15, 00 RF_CLIF_CFG_BR_848_I_TXB CLIF_TX_OVERSHOOT_CONFIG_REG
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# A0, 0D, 06, 56, 2D, 05, 9E, 0C, 00 RF_CLIF_CFG_BR_212_I_RXF_P CLIF_SIGPRO_RM_CONFIG1_REG
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# A0, 0D, 04, 56, 44, 22, 00 RF_CLIF_CFG_BR_212_I_RXF_P CLIF_ANA_RX_REG
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# A0, 0D, 06, 5C, 2D, 05, 9E, 0C, 00 RF_CLIF_CFG_BR_424_I_RXF_P CLIF_SIGPRO_RM_CONFIG1_REG
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# A0, 0D, 04, 5C, 44, 26, 00 RF_CLIF_CFG_BR_424_I_RXF_P CLIF_ANA_RX_REG
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# A0, 0D, 06, 54, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_212_I_TXF CLIF_ANA_TX_AMPLITUDE_REG
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# A0, 0D, 06, 54, 4A, 33, 07, 01, 07 RF_CLIF_CFG_BR_212_I_TXF CLIF_ANA_TX_SHAPE_CONTROL_REG
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# A0, 0D, 03, 54, 16, 00 RF_CLIF_CFG_BR_212_I_TXF CLIF_TX_UNDERSHOOT_CONFIG_REG
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# A0, 0D, 03, 54, 15, 00 RF_CLIF_CFG_BR_212_I_TXF CLIF_TX_OVERSHOOT_CONFIG_REG
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# A0, 0D, 06, 5A, 42, 90, 10, FF, FF RF_CLIF_CFG_BR_424_I_TXF CLIF_ANA_TX_AMPLITUDE_REG
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# A0, 0D, 06, 5A, 4A, 31, 07, 01, 07 RF_CLIF_CFG_BR_424_I_TXF CLIF_ANA_TX_SHAPE_CONTROL_REG
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# A0, 0D, 03, 5A, 16, 00 RF_CLIF_CFG_BR_424_I_TXF CLIF_TX_UNDERSHOOT_CONFIG_REG
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# A0, 0D, 03, 5A, 15, 00 RF_CLIF_CFG_BR_424_I_TXF CLIF_TX_OVERSHOOT_CONFIG_REG
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# A0, 0D, 06, 98, 2F, CF, 05, 80, 17 RF_CLIF_CFG_GTM_B CLIF_SIGPRO_ADCBCM_CONFIG_REG
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# A0, 0D, 06, 98, 42, 00, 02, FF, FF RF_CLIF_CFG_GTM_B CLIF_ANA_TX_AMPLITUDE_REG
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# A0, 0D, 06, 9A, 42, 00, 02, FF, FF RF_CLIF_CFG_GTM_FELICA CLIF_ANA_TX_AMPLITUDE_REG
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# A0, 0D, 06, 30, 44, 12, 90, 03, 00 RF_CLIF_CFG_TECHNO_T_RXF CLIF_ANA_RX_REG
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# A0, 0D, 06, 6C, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_106_T_RXA CLIF_ANA_RX_REG
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# A0, 0D, 06, 6C, 30, CF, 00, 08, 00 RF_CLIF_CFG_BR_106_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
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# A0, 0D, 06, 6C, 2F, 8F, 05, 80, 0C RF_CLIF_CFG_BR_106_T_RXA CLIF_SIGPRO_ADCBCM_CONFIG_REG
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# A0, 0D, 06, 70, 2F, 8F, 05, 80, 12 RF_CLIF_CFG_BR_212_T_RXA CLIF_SIGPRO_ADCBCM_CONFIG_REG
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# A0, 0D, 06, 70, 30, CF, 00, 08, 00 RF_CLIF_CFG_BR_212_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
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# A0, 0D, 03, 70, 2E, 40 RF_CLIF_CFG_BR_212_T_RXA CLIF_SIGPRO_CM_CONFIG_REG
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# A0, 0D, 03, 70, 45, 30 RF_CLIF_CFG_BR_212_T_RXA CLIF_ANA_CM_CONFIG_REG
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# A0, 0D, 06, 70, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_212_T_RXA CLIF_ANA_RX_REG
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# A0, 0D, 06, 74, 2F, 6F, 05, 80, 12 RF_CLIF_CFG_BR_424_T_RXA CLIF_SIGPRO_ADCBCM_CONFIG_REG
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# A0, 0D, 06, 74, 30, D5, 00, 40, 00 RF_CLIF_CFG_BR_424_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
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# A0, 0D, 06, 74, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_424_T_RXA CLIF_ANA_RX_REG
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# A0, 0D, 06, 78, 2F, 3F, 07, 80, C1 RF_CLIF_CFG_BR_848_T_RXA CLIF_SIGPRO_ADCBCM_CONFIG_REG
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# A0, 0D, 06, 78, 30, 50, 00, 10, 00 RF_CLIF_CFG_BR_848_T_RXA CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
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# A0, 0D, 06, 78, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_848_T_RXA CLIF_ANA_RX_REG
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# A0, 0D, 06, 7C, 2F, CF, 05, 80, 17 RF_CLIF_CFG_BR_106_T_RXB CLIF_SIGPRO_ADCBCM_CONFIG_REG
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# A0, 0D, 06, 7C, 30, C8, 00, 64, 00 RF_CLIF_CFG_BR_106_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
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# A0, 0D, 06, 7C, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_106_T_RXB CLIF_ANA_RX_REG
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# A0, 0D, 06, 80, 2F, CF, 05, 80, 17 RF_CLIF_CFG_BR_212_T_RXB CLIF_SIGPRO_ADCBCM_CONFIG_REG
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# A0, 0D, 06, 80, 30, C8, 00, 64, 00 RF_CLIF_CFG_BR_212_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
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# A0, 0D, 06, 80, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_212_T_RXB CLIF_ANA_RX_REG
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# A0, 0D, 06, 84, 2F, CF, 05, 80, 17 RF_CLIF_CFG_BR_424_T_RXB CLIF_SIGPRO_ADCBCM_CONFIG_REG
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# A0, 0D, 06, 84, 30, C8, 00, 64, 00 RF_CLIF_CFG_BR_424_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
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# A0, 0D, 06, 84, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_424_T_RXB CLIF_ANA_RX_REG
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# A0, 0D, 06, 88, 2F, B1, 05, 80, 17 RF_CLIF_CFG_BR_848_T_RXB CLIF_SIGPRO_ADCBCM_CONFIG_REG
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# A0, 0D, 06, 88, 30, A8, 00, 64, 00 RF_CLIF_CFG_BR_848_T_RXB CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
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# A0, 0D, 06, 88, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_848_T_RXB CLIF_ANA_RX_REG
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# A0, 0D, 06, 8E, 44, 12, 90, 03, 00 RF_CLIF_CFG_BR_212_T_RXF CLIF_ANA_RX_REG
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# A0, 0D, 06, 94, 44, 12, 90, 03, 00 RF_CLIF_CFG_BR_424_T_RXF CLIF_ANA_RX_REG
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# A0, 0D, 03, 10, 43, 20 RF_CLIF_CFG_T_ACTIVE CLIF_ANA_PBF_CONTROL_REG
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# A0, 0D, 06, 10, 35, FF, 01, FF, 02 RF_CLIF_CFG_T_ACTIVE CLIF_AGC_INPUT_REG
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# A0, 0D, 06, 10, 34, F7, 7F, 00, 00 RF_CLIF_CFG_T_ACTIVE CLIF_AGC_CONFIG1_REG
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# A0, 0D, 06, 6A, 42, F8, 10, FF, FF RF_CLIF_CFG_BR_106_T_TXA_A CLIF_ANA_TX_AMPLITUDE_REG
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# A0, 0D, 03, 6A, 16, 00 RF_CLIF_CFG_BR_106_T_TXA_A CLIF_TX_UNDERSHOOT_CONFIG_REG
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# A0, 0D, 03, 6A, 15, 01 RF_CLIF_CFG_BR_106_T_TXA_A CLIF_TX_OVERSHOOT_CONFIG_REG
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# A0, 0D, 06, 6A, 4A, 30, 0F, 01, 1F RF_CLIF_CFG_BR_106_T_TXA_A CLIF_ANA_TX_SHAPE_CONTROL_REG
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# A0, 0D, 06, 8C, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_212_T_TXF_A CLIF_ANA_TX_AMPLITUDE_REG
|
|
# A0, 0D, 06, 8C, 4A, 33, 07, 01, 07 RF_CLIF_CFG_BR_212_T_TXF_A CLIF_ANA_TX_SHAPE_CONTROL_REG
|
|
# A0, 0D, 03, 8C, 16, 00 RF_CLIF_CFG_BR_212_T_TXF_A CLIF_TX_UNDERSHOOT_CONFIG_REG
|
|
# A0, 0D, 03, 8C, 15, 00 RF_CLIF_CFG_BR_212_T_TXF_A CLIF_TX_OVERSHOOT_CONFIG_REG
|
|
# A0, 0D, 06, 92, 42, 90, 10, FF, FF RF_CLIF_CFG_BR_424_T_TXF_A CLIF_ANA_TX_AMPLITUDE_REG
|
|
# A0, 0D, 06, 92, 4A, 31, 07, 01, 07 RF_CLIF_CFG_BR_424_T_TXF_A CLIF_ANA_TX_SHAPE_CONTROL_REG
|
|
# A0, 0D, 03, 92, 16, 00 RF_CLIF_CFG_BR_424_T_TXF_A CLIF_TX_UNDERSHOOT_CONFIG_REG
|
|
# A0, 0D, 03, 92, 15, 00 RF_CLIF_CFG_BR_424_T_TXF_A CLIF_TX_OVERSHOOT_CONFIG_REG
|
|
# A0, 0D, 03, 24, 41, 40 RF_CLIF_CFG_TECHNO_T_TXA_P CLIF_ANA_TX_CLK_CONTROL_REG
|
|
# A0, 0D, 06, 24, 42, 00, 02, FF, FF RF_CLIF_CFG_TECHNO_T_TXA_P CLIF_ANA_TX_AMPLITUDE_REG
|
|
# A0, 0D, 03, 28, 41, 40 RF_CLIF_CFG_TECHNO_T_TXB CLIF_ANA_TX_CLK_CONTROL_REG
|
|
# A0, 0D, 03, 8A, 41, 40 RF_CLIF_CFG_BR_212_T_TXF_P CLIF_ANA_TX_CLK_CONTROL_REG
|
|
# A0, 0D, 03, 90, 41, 40 RF_CLIF_CFG_BR_424_T_TXF_P CLIF_ANA_TX_CLK_CONTROL_REG
|
|
# A0, 0D, 03, 08, 40, 10 RF_CLIF_CFG_I_PASSIVE CLIF_ANA_NFCLD_REG
|
|
# A0, 0D, 06, 08, 45, C0, 82, 00, 00 RF_CLIF_CFG_I_PASSIVE CLIF_ANA_CM_CONFIG_REG
|
|
# A0, 0D, 06, 0A, 44, A3, 90, 03, 00 RF_CLIF_CFG_I_ACTIVE CLIF_ANA_RX_REG
|
|
# A0, 0D, 06, 0A, 45, 80, 40, 00, 00 RF_CLIF_CFG_I_ACTIVE CLIF_ANA_CM_CONFIG_REG
|
|
# A0, 0D, 06, 0A, 30, C8, 00, 64, 00 RF_CLIF_CFG_I_ACTIVE CLIF_SIGPRO_ADCBCM_THRESHOLD_REG
|
|
# A0, 0D, 06, 0A, 2F, AF, 05, 80, 17 RF_CLIF_CFG_I_ACTIVE CLIF_SIGPRO_ADCBCM_CONFIG_REG
|
|
# A0, 0D, 03, 0A, 48, 10 RF_CLIF_CFG_I_ACTIVE CLIF_ANA_CLK_MAN_REG
|
|
# A0, 0D, 06, 0A, 34, 26, 65, E5, 03 RF_CLIF_CFG_I_ACTIVE CLIF_AGC_CONFIG1_REG
|
|
# A0, 0D, 06, 0A, 33, 0F, 01, 00, 70 RF_CLIF_CFG_I_ACTIVE CLIF_AGC_CONFIG0_REG
|
|
# A0, 0D, 03, 0A, 40, 00 RF_CLIF_CFG_I_ACTIVE CLIF_ANA_NFCLD_REG
|
|
#
|
|
# *** ALMSL FW VERSION = 10.05.03 ***
|
|
NXP_RF_CONF_BLK_1={
|
|
20, 02, FA, 20,
|
|
A0, 0D, 03, 00, 40, 03,
|
|
A0, 0D, 06, 00, FF, 05, 04, 06, 00,
|
|
A0, 0D, 06, 00, 35, FF, 01, FF, 02,
|
|
A0, 0D, 06, 00, 33, 07, 40, 00, 00,
|
|
A0, 0D, 03, 02, 40, 00,
|
|
A0, 0D, 03, 04, 43, 20,
|
|
A0, 0D, 03, 04, 47, 02,
|
|
A0, 0D, 06, 04, 35, F4, 01, F4, 01,
|
|
A0, 0D, 06, 04, FF, 05, 00, 00, 00,
|
|
A0, 0D, 06, 05, 45, 80, 40, 00, 00,
|
|
A0, 0D, 06, 05, 35, FF, 01, FF, 02,
|
|
A0, 0D, 06, 05, 33, 07, 40, 00, 00,
|
|
A0, 0D, 06, 06, 44, A3, 90, 03, 00,
|
|
A0, 0D, 03, 06, 47, 02,
|
|
A0, 0D, 06, 06, 35, C0, 03, C0, 02,
|
|
A0, 0D, 06, 06, 34, F7, 7F, 00, 10,
|
|
A0, 0D, 06, 06, 33, 03, 40, 00, 00,
|
|
A0, 0D, 06, 06, 30, B0, 00, 10, 00,
|
|
A0, 0D, 06, 06, 2F, AF, 05, 80, 17,
|
|
A0, 0D, 06, 06, 03, 00, 71, 00, 20,
|
|
A0, 0D, 03, 06, 43, 20,
|
|
A0, 0D, 06, 06, 42, 00, 03, F2, F2,
|
|
A0, 0D, 03, 06, 41, 40,
|
|
A0, 0D, 03, 06, 37, 08,
|
|
A0, 0D, 03, 06, 16, 00,
|
|
A0, 0D, 03, 06, 15, 00,
|
|
A0, 0D, 03, 06, 3F, 04,
|
|
A0, 0D, 03, 06, 80, 03,
|
|
A0, 0D, 06, 06, FF, 05, 00, 00, 00,
|
|
A0, 0D, 03, 07, 3F, 00,
|
|
A0, 0D, 06, 07, 35, FF, 01, FF, 02,
|
|
A0, 0D, 06, 07, 33, 07, 40, 00, 00
|
|
}
|
|
|
|
NXP_RF_CONF_BLK_2={
|
|
20, 02, F8, 1F,
|
|
A0, 0D, 06, 18, 34, 00, 00, E1, 03,
|
|
A0, 0D, 06, 18, 33, 0F, 83, 00, 00,
|
|
A0, 0D, 06, 1C, 34, 00, 00, E1, 03,
|
|
A0, 0D, 06, 1C, 33, 0F, 83, 00, 00,
|
|
A0, 0D, 06, 20, 4A, 00, 00, 00, 00,
|
|
A0, 0D, 06, 20, 42, 88, 10, FF, FF,
|
|
A0, 0D, 03, 20, 16, 00,
|
|
A0, 0D, 03, 20, 15, 00,
|
|
A0, 0D, 04, 22, 44, 22, 00,
|
|
A0, 0D, 06, 22, 2D, 50, 44, 0C, 00,
|
|
A0, 0D, 04, 32, 03, 40, 3D,
|
|
A0, 0D, 06, 32, 42, F8, 10, FF, FF,
|
|
A0, 0D, 03, 32, 16, 00,
|
|
A0, 0D, 03, 32, 15, 01,
|
|
A0, 0D, 03, 32, 0D, 22,
|
|
A0, 0D, 03, 32, 14, 22,
|
|
A0, 0D, 06, 32, 4A, 33, 07, 00, 08,
|
|
A0, 0D, 06, 34, 2D, 24, 47, 0C, 00,
|
|
A0, 0D, 06, 34, 34, 00, 00, EC, 03,
|
|
A0, 0D, 06, 34, 33, 0F, 01, 01, 70,
|
|
A0, 0D, 04, 34, 44, 21, 00,
|
|
A0, 0D, 06, 38, 4A, 33, 07, 00, 08,
|
|
A0, 0D, 06, 38, 42, 68, 10, FF, FF,
|
|
A0, 0D, 03, 38, 16, 00,
|
|
A0, 0D, 03, 38, 15, 00,
|
|
A0, 0D, 04, 3A, 44, 26, 00,
|
|
A0, 0D, 06, 3A, 2D, 15, 47, 0D, 00,
|
|
A0, 0D, 06, 3A, 34, 00, 00, E1, 03,
|
|
A0, 0D, 06, 3A, 33, 0B, 83, 00, 00,
|
|
A0, 0D, 06, 3C, 4A, 52, 07, 00, 1B,
|
|
A0, 0D, 06, 3C, 42, 68, 10, FF, FF
|
|
}
|
|
|
|
NXP_RF_CONF_BLK_3={
|
|
20, 02, F9, 20,
|
|
A0, 0D, 03, 3C, 16, 00,
|
|
A0, 0D, 03, 3C, 15, 00,
|
|
A0, 0D, 04, 3E, 44, 26, 00,
|
|
A0, 0D, 06, 3E, 2D, 15, 47, 0D, 00,
|
|
A0, 0D, 06, 3E, 34, 00, 00, E1, 03,
|
|
A0, 0D, 06, 3E, 33, 0B, 83, 00, 00,
|
|
A0, 0D, 06, 40, 42, F0, 10, FF, FF,
|
|
A0, 0D, 03, 40, 0D, 02,
|
|
A0, 0D, 03, 40, 14, 02,
|
|
A0, 0D, 06, 40, 4A, 12, 07, 00, 00,
|
|
A0, 0D, 03, 40, 16, 00,
|
|
A0, 0D, 03, 40, 15, 00,
|
|
A0, 0D, 04, 42, 44, 26, 00,
|
|
A0, 0D, 06, 42, 2D, 15, 47, 0D, 00,
|
|
A0, 0D, 06, 42, 34, 00, 00, E1, 03,
|
|
A0, 0D, 06, 42, 33, 0B, 83, 00, 00,
|
|
A0, 0D, 04, 46, 44, 26, 00,
|
|
A0, 0D, 06, 46, 2D, 15, 25, 0D, 00,
|
|
A0, 0D, 06, 44, 4A, 21, 07, 00, 07,
|
|
A0, 0D, 06, 44, 42, 88, 10, FF, FF,
|
|
A0, 0D, 03, 44, 16, 00,
|
|
A0, 0D, 03, 44, 15, 00,
|
|
A0, 0D, 04, 4A, 44, 21, 00,
|
|
A0, 0D, 06, 4A, 2D, 15, 9D, 0D, 00,
|
|
A0, 0D, 06, 48, 4A, 21, 07, 00, 07,
|
|
A0, 0D, 06, 48, 42, 88, 10, FF, FF,
|
|
A0, 0D, 03, 48, 16, 00,
|
|
A0, 0D, 03, 48, 15, 00,
|
|
A0, 0D, 04, 4E, 44, 26, 00,
|
|
A0, 0D, 06, 4E, 2D, 15, 25, 0D, 00,
|
|
A0, 0D, 06, 4C, 4A, 21, 07, 00, 07,
|
|
A0, 0D, 06, 4C, 42, 88, 10, FF, FF
|
|
}
|
|
|
|
NXP_RF_CONF_BLK_4={
|
|
20, 02, F4, 1F,
|
|
A0, 0D, 03, 4C, 16, 00,
|
|
A0, 0D, 03, 4C, 15, 00,
|
|
A0, 0D, 04, 52, 44, 26, 00,
|
|
A0, 0D, 06, 52, 2D, 15, 25, 0D, 00,
|
|
A0, 0D, 06, 50, 42, 90, 10, FF, FF,
|
|
A0, 0D, 06, 50, 4A, 21, 07, 00, 07,
|
|
A0, 0D, 03, 50, 16, 00,
|
|
A0, 0D, 03, 50, 15, 00,
|
|
A0, 0D, 06, 56, 2D, 05, 9E, 0C, 00,
|
|
A0, 0D, 04, 56, 44, 22, 00,
|
|
A0, 0D, 06, 5C, 2D, 05, 9E, 0C, 00,
|
|
A0, 0D, 04, 5C, 44, 26, 00,
|
|
A0, 0D, 06, 54, 42, 88, 10, FF, FF,
|
|
A0, 0D, 06, 54, 4A, 33, 07, 01, 07,
|
|
A0, 0D, 03, 54, 16, 00,
|
|
A0, 0D, 03, 54, 15, 00,
|
|
A0, 0D, 06, 5A, 42, 90, 10, FF, FF,
|
|
A0, 0D, 06, 5A, 4A, 31, 07, 01, 07,
|
|
A0, 0D, 03, 5A, 16, 00,
|
|
A0, 0D, 03, 5A, 15, 00,
|
|
A0, 0D, 06, 98, 2F, CF, 05, 80, 17,
|
|
A0, 0D, 06, 98, 42, 00, 03, F2, F2,
|
|
A0, 0D, 06, 9A, 42, 00, 03, F2, F2,
|
|
A0, 0D, 06, 30, 44, 12, 90, 03, 00,
|
|
A0, 0D, 06, 6C, 44, A3, 90, 03, 00,
|
|
A0, 0D, 06, 6C, 30, CF, 00, 08, 00,
|
|
A0, 0D, 06, 6C, 2F, 8F, 05, 80, 0C,
|
|
A0, 0D, 06, 70, 2F, 8F, 05, 80, 12,
|
|
A0, 0D, 06, 70, 30, CF, 00, 08, 00,
|
|
A0, 0D, 03, 70, 2E, 40,
|
|
A0, 0D, 03, 70, 45, 30
|
|
}
|
|
|
|
NXP_RF_CONF_BLK_5={
|
|
20, 02, F4, 1C,
|
|
A0, 0D, 06, 70, 44, A3, 90, 03, 00,
|
|
A0, 0D, 06, 74, 2F, 6F, 05, 80, 12,
|
|
A0, 0D, 06, 74, 30, D5, 00, 40, 00,
|
|
A0, 0D, 06, 74, 44, A3, 90, 03, 00,
|
|
A0, 0D, 06, 78, 2F, 3F, 07, 80, C1,
|
|
A0, 0D, 06, 78, 30, 50, 00, 10, 00,
|
|
A0, 0D, 06, 78, 44, A3, 90, 03, 00,
|
|
A0, 0D, 06, 7C, 2F, CF, 05, 80, 17,
|
|
A0, 0D, 06, 7C, 30, B0, 00, 10, 00,
|
|
A0, 0D, 06, 7C, 44, A3, 90, 03, 00,
|
|
A0, 0D, 06, 80, 2F, CF, 05, 80, 17,
|
|
A0, 0D, 06, 80, 30, C8, 00, 64, 00,
|
|
A0, 0D, 06, 80, 44, A3, 90, 03, 00,
|
|
A0, 0D, 06, 84, 2F, CF, 05, 80, 17,
|
|
A0, 0D, 06, 84, 30, C8, 00, 64, 00,
|
|
A0, 0D, 06, 84, 44, A3, 90, 03, 00,
|
|
A0, 0D, 06, 88, 2F, B1, 05, 80, 17,
|
|
A0, 0D, 06, 88, 30, A8, 00, 64, 00,
|
|
A0, 0D, 06, 88, 44, A3, 90, 03, 00,
|
|
A0, 0D, 06, 8E, 44, 12, 90, 03, 00,
|
|
A0, 0D, 06, 94, 44, 12, 90, 03, 00,
|
|
A0, 0D, 03, 10, 43, 20,
|
|
A0, 0D, 06, 10, 35, FF, 01, FF, 02,
|
|
A0, 0D, 06, 10, 34, F7, 7F, 00, 00,
|
|
A0, 0D, 06, 6A, 42, F8, 10, FF, FF,
|
|
A0, 0D, 03, 6A, 16, 00,
|
|
A0, 0D, 03, 6A, 15, 01,
|
|
A0, 0D, 06, 6A, 4A, 30, 0F, 01, 1F
|
|
}
|
|
|
|
NXP_RF_CONF_BLK_6={
|
|
20, 02, AF, 17,
|
|
A0, 0D, 06, 8C, 42, 88, 10, FF, FF,
|
|
A0, 0D, 06, 8C, 4A, 33, 07, 01, 07,
|
|
A0, 0D, 03, 8C, 16, 00,
|
|
A0, 0D, 03, 8C, 15, 00,
|
|
A0, 0D, 06, 92, 42, 90, 10, FF, FF,
|
|
A0, 0D, 06, 92, 4A, 31, 07, 01, 07,
|
|
A0, 0D, 03, 92, 16, 00,
|
|
A0, 0D, 03, 92, 15, 00,
|
|
A0, 0D, 03, 24, 41, 40,
|
|
A0, 0D, 06, 24, 42, 00, 03, F2, F2,
|
|
A0, 0D, 03, 28, 41, 40,
|
|
A0, 0D, 03, 8A, 41, 40,
|
|
A0, 0D, 03, 90, 41, 40,
|
|
A0, 0D, 03, 08, 40, 10,
|
|
A0, 0D, 06, 08, 45, C0, 82, 00, 00,
|
|
A0, 0D, 06, 0A, 44, A3, 90, 03, 00,
|
|
A0, 0D, 06, 0A, 45, 80, 40, 00, 00,
|
|
A0, 0D, 06, 0A, 30, C8, 00, 64, 00,
|
|
A0, 0D, 06, 0A, 2F, AF, 05, 80, 17,
|
|
A0, 0D, 03, 0A, 48, 10,
|
|
A0, 0D, 06, 0A, 34, 26, 65, E5, 03,
|
|
A0, 0D, 06, 0A, 33, 0F, 01, 00, 70,
|
|
A0, 0D, 03, 0A, 40, 00
|
|
}
|
|
|
|
|
|
###############################################################################
|
|
|
|
|
|
|
|
|
|
###############################################################################
|
|
# Core configuration extensions
|
|
# It includes
|
|
# A002 - Disable/Enable Clock Request
|
|
# A009 - Time-out before standby
|
|
# A012 - NFCEE interface 2 configuration
|
|
# A040 - Low Power Card Detector Enable
|
|
# A041 - Low Power Card Detector Threshold
|
|
# A042 - Low Power Card Detector Sampling
|
|
# A043 - Low Power Card Detector Hybrid
|
|
# A05E - Send RID automatically in Jewel Reader mode
|
|
# A061 - Retry after LPCD
|
|
# A096 - Notify all AIDs
|
|
# A0DD - Retry on SWP2 interface
|
|
# A0EC - Disable/Enable SWP1 interface
|
|
# A0ED - Disable/Enable SWP2 interface
|
|
# A0F2 - SVDD_PWR_REQ enable
|
|
NXP_CORE_CONF_EXTN={20, 02, B3, 13,
|
|
A0, 02, 01, 01,
|
|
A0, 09, 02, E8, 03,
|
|
A0, 12, 01, 00,
|
|
A0, 40, 01, 01,
|
|
A0, 41, 01, 05,
|
|
A0, 42, 01, 0F,
|
|
A0, 43, 01, 03,
|
|
A0, 5E, 01, 01,
|
|
A0, 61, 01, 53,
|
|
A0, 96, 01, 01,
|
|
A0, DD, 01, 2D,
|
|
A0, EC, 01, 01,
|
|
A0, ED, 01, 00,
|
|
A0, F2, 01, 00,
|
|
A0, 47, 02, 00, 32,
|
|
A0, D5, 01, 04,
|
|
A0, 1D, 11, 51, 33, 14, 17, 00, AA, 85, 00, 80, 55, 2A, 04, 00, 63, 00, 00, 00,
|
|
A0, 1E, 11, 1B, 13, 14, 14, 00, 6F, 97, 00, 00, 00, 10, 04, 00, 63, 02, 00, 00,
|
|
A0, 92, 45, 23, 04, 50, 10, 00, 00, 00, 14, 00, 20, 00, 14, 00, B3, 00, 06, 00, 20, 01, 06, 00, FF, 03, 06, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00
|
|
}
|
|
|
|
|
|
###############################################################################
|
|
# Core configuration extensions
|
|
# It includes
|
|
# A002 - Disable/Enable Clock Request
|
|
# A009 - Time-out before standby
|
|
# A012 - NFCEE interface 2 configuration
|
|
# A040 - Low Power Card Detector Enable
|
|
# A041 - Low Power Card Detector Threshold
|
|
# A042 - Low Power Card Detector Sampling
|
|
# A043 - Low Power Card Detector Hybrid
|
|
# A05E - Send RID automatically in Jewel Reader mode
|
|
# A061 - Retry after LPCD
|
|
# A096 - Notify all AIDs
|
|
# A0DD - Retry on SWP2 interface
|
|
# A0EC - Disable/Enable SWP1 interface
|
|
# A0ED - Disable/Enable SWP2 interface
|
|
# A0F2 - SVDD_PWR_REQ enable
|
|
NXP_CORE_CONF_EXTN={20, 02, B7, 14,
|
|
A0, 02, 01, 01,
|
|
A0, 09, 02, E8, 03,
|
|
A0, 12, 01, 00,
|
|
A0, 40, 01, 01,
|
|
A0, 41, 01, 05,
|
|
A0, 42, 01, 0F,
|
|
A0, 43, 01, 03,
|
|
A0, 5E, 01, 01,
|
|
A0, 61, 01, 53,
|
|
A0, 96, 01, 01,
|
|
A0, DD, 01, 2D,
|
|
A0, EC, 01, 01,
|
|
A0, ED, 01, 00,
|
|
A0, F2, 01, 00,
|
|
A0, 47, 02, 00, 27,
|
|
A0, CD, 01, 1F,
|
|
A0, CB, 01, 10,
|
|
A0, 1D, 11, 52, 33, 14, 17, 00, AA, 85, 00, 80, 55, 2A, 04, 00, 63, 00, 00, 00,
|
|
A0, 1E, 11, 1B, 13, 14, 14, 00, 6F, 97, 00, 00, 00, 10, 04, 00, 63, 02, 00, 00,
|
|
A0, 92, 45, 23, 04, 50, 10, 00, 00, 00, 14, 00, 20, 00, 14, 00, B3, 00, 06, 00, 20, 01, 06, 00, FF, 03, 06, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00
|
|
}
|
|
|
|
|
|
###############################################################################
|
|
# Core configuration settings
|
|
# It includes
|
|
# 18 - Poll Mode NFC-F: PF_BIT_RATE
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# 21 - Poll Mode ISO-DEP: PI_BIT_RATE
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# 28 - Poll Mode NFC-DEP: PN_NFC_DEP_SPEED
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# 30 - Lis. Mode NFC-A: LA_BIT_FRAME_SDD
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# 31 - Lis. Mode NFC-A: LA_PLATFORM_CONFIG
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# 33 - Lis. Mode NFC-A: LA_NFCID1
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# 50 - Lis. Mode NFC-F: LF_PROTOCOL_TYPE
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# 54 - Lis. Mode NFC-F: LF_CON_BITR_F
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# 5B - Lis. Mode ISO-DEP: LI_BIT_RATE
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# 60 - Lis. Mode NFC-DEP: LN_WT
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# 80 - Other Param.: RF_FIELD_INFO
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# 81 - Other Param.: RF_NFCEE_ACTION
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# 82 - Other Param.: NFCDEP_OP
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NXP_CORE_CONF={20, 02, 2A, 0E,
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18, 01, 01,
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21, 01, 00,
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28, 01, 00,
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30, 01, 04,
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31, 01, 00,
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33, 00,
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50, 01, 02,
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54, 01, 06,
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5B, 01, 00,
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60, 01, 0E,
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80, 01, 01,
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81, 01, 01,
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82, 01, 0E,
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|
32, 01, 60
|
|
}
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